POP Semiconductor Package Layout for Heat Dissipation Paths
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Solution Overview
Problem
The challenge of effectively dissipating heat generated from high-calorific value chips in Package-On-Package (POP) semiconductor structures is exacerbated by the placement of upper packages, which hinders efficient heat dissipation and increases electrical connection path lengths.
Innovation Solution
A semiconductor package design featuring a first and second redistribution structure with encapsulants and conductive posts that integrate semiconductor chips and passive components, allowing for vertical overlap and reduced electrical connection paths, along with direct thermal interface material bonding to enhance heat dissipation and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an upper package is placed on a lower package in a vertically oriented arrangement, then miniaturization of electronic devices is achieved, but heat dissipation from high-calorific value chips is hindered
Solution Approach 1:
The patent transitions from a traditional side-by-side horizontal arrangement to a vertically stacked three-dimensional configuration. The lower package contains the application processor chip while the upper package contains the memory chip, utilizing the vertical dimension to achieve miniaturization. This spatial reorganization allows heat to be dissipated through multiple surfaces (top, bottom, and sides) rather than being constrained to a single plane, thereby maintaining effective heat dissipation despite the compact vertical arrangement.
2Volume of moving object
If an upper package is placed on a lower package, then device miniaturization is achieved, but electrical connection path length increases
Solution Approach 1:
By stacking packages vertically, the electrical connection path is optimized through direct vertical alignment between corresponding pads on the lower and upper packages. The connection path travels through the thickness of the packages and encapsulant material rather than requiring long lateral traces, significantly reducing the overall electrical connection length despite the three-dimensional configuration.
Solution Approach 2:
The encapsulant material serving as the lower package's upper surface acts as an intermediary that provides both mechanical support and electrical connection functionality. The conductive paths are embedded within or on the surface of this encapsulant, creating direct electrical pathways between the lower package chips and upper package chips without requiring extended external connection traces.
3Area of stationary object
If packages are stacked vertically, then space is saved, but heat dissipation efficiency decreases
Solution Approach 1:
The vertical stacking configuration utilizes the third dimension (height) to reduce the footprint area while maintaining effective heat dissipation. Heat can escape through the top surface of the upper package, the bottom surface of the lower package, and the lateral surfaces of both packages, providing multiple thermal escape routes that compensate for the reduced horizontal area.
Data Source
AI summary
A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.