POP Package with Multiplexed Memory Interface and Mechanical Solder Balls
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Solution Overview
Problem
Current package-on-package (POP) devices lack optimized high-frequency and high-bus-width interfaces, are limited to single mass memory support, and suffer from mechanical reliability issues due to the number and location of solder balls.
Innovation Solution
A semiconductor device with a memory IC package stacked above an ASIC IC package, featuring a flash memory I/O bus that multiplexes NAND and NOR memory signals, reducing external terminal count and enabling choice between memory types, while using solder balls for mechanical support without live connections, thus enhancing mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are used for interconnection between memory IC and ASIC IC, then electrical connection is achieved, but mechanical reliability deteriorates due to stress concentration at solder ball locations
Solution Approach 1:
The patent extracts the mechanical support function from the electrical interconnection function by designating specific solder balls as mechanical support only (not connected electrically). These NC solder balls are positioned at stress-prone locations to bear mechanical loads without transmitting electrical signals, thereby separating the two functions and reducing stress concentration on active interconnection solder balls.
2Adaptability or versatility
If separate pins are provided for NAND and NOR flash memory, then adaptability to different memory types is improved, but device complexity increases due to higher pin count
Solution Approach 1:
The patent implements universality by designing a unified external terminal layout that can accommodate both NAND and NOR flash memory interfaces. The same physical pins are configured through software or configuration bits to support different memory types, eliminating the need for separate pin sets and reducing overall device complexity while maintaining adaptability.
Solution Approach 2:
The patent employs dynamic configuration where the function of external terminals can be changed based on the detected memory type. The system dynamically adjusts the I/O bus configuration and pin assignments according to whether NAND or NOR memory is detected, allowing flexible adaptation without fixed hardware constraints.
3Ease of manufacture
If area array type package is used with all I/O contacts on one surface, then manufacturing ease is improved, but adaptability for stacking and through-access deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional area array layout to a three-dimensional stacked configuration. I/O contacts are distributed across multiple surfaces and layers, with some contacts on the top surface and others on the bottom surface, enabling vertical stacking of multiple packages while maintaining manufacturing feasibility through extended bump array techniques.
Solution Approach 2:
The patent segments the I/O contacts into different groups located on different surfaces of the package. This segmentation allows independent access to different contact groups from different directions, facilitating package-on-package stacking where upper packages connect to specific contacts on the lower package while maintaining manufacturing simplicity for each individual package.
Data Source
AI summary
An integrated circuit package comprising: an substrate having a first main surface and a second main surface which are opposite to each other; a first plurality of external terminals disposed on the first main surface of said interconnection substrate; and a second plurality of external terminals disposed on the second main surface of said interconnection substrate; wherein said second plurality of external terminals comprises a predefined selection of shared external terminals defining a first interface for an integrated circuit memory package having type NAND or type NOR memory.