POP Semiconductor Package Bonding Layer for Thermal Mismatch
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Solution Overview
Problem
The semiconductor industry faces challenges in managing thermal expansion mismatch between different materials in semiconductor package devices, which can lead to delamination and reliability issues in Package-on-Package (POP) technology.
Innovation Solution
A layer of thermal expansion resistant material is deposited at bonding boundary points within the semiconductor package device, helping to alleviate strain caused by thermal mismatch between materials. This layer, typically made of materials like silicon nitride, has a hardness range of 10 GPa to 30 GPa, effectively suppressing punch up and reducing the risk of delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (POP) technology is used to increase integration density, then component density and functionality are improved, but thermal expansion mismatch between materials causes delamination and reliability issues
Solution Approach 1:
A thermal expansion resistant layer is introduced as an intermediary between the bottom semiconductor die and the top semiconductor package. This layer acts as a mediator that absorbs and distributes thermal stress, preventing direct transmission of thermal expansion forces that would cause delamination at the bonding interfaces.
Solution Approach 2:
The patent modifies the physical parameters of the package structure by incorporating a layer with specific thermal expansion properties (resistant to thermal expansion). This changes the overall thermal behavior of the package, allowing it to withstand thermal cycling without delamination while maintaining high integration density through POP architecture.
2Quantity of substance
If multiple semiconductor dies are stacked in POP configuration, then integration density increases, but thermal strain from material mismatch causes structural integrity issues
Solution Approach 1:
The thermal expansion resistant layer serves as a structural intermediary that decouples the thermal expansion behavior of different semiconductor materials. By positioning this layer at critical bonding interfaces, it prevents stress concentration and maintains structural integrity throughout the stacked POP configuration.
Solution Approach 2:
The patent employs a composite structure combining multiple materials with different thermal expansion properties. The thermal expansion resistant layer is integrated with semiconductor dies and packaging materials to create a composite structure that leverages the advantageous properties of each material while compensating for their individual weaknesses regarding thermal mismatch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a thermal expansion resistant layer improves the reliability of POP devices by reducing the risk of delamination and enhancing the structural integrity of the semiconductor package, thereby supporting the integration of more complex and densely packed electronic components.
Implementation Method 1
a layer of thermal expansion resistant material is deposited at bonding boundary points within the semiconductor package device. The layer of thermal expansion resistant material helps alleviate the strain caused between the thermal mismatch between materials
Data Source
AI summary
A semiconductor device and methods of manufacture are discussed herein. A device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.