POP Package Structure with TIV Interconnects for Delamination Control
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently connecting and integrating multiple semiconductor dies within a package structure, particularly in achieving reliable electrical connections and minimizing delamination stresses, which can impact the performance and reliability of Package-on-Package (POP) structures.
Innovation Solution
The method involves using through insulator vias (TIVs) and a debond layer on a carrier, followed by encapsulation and redistribution layers, with solder joints formed between packages, and an underfill material to manage stress and ensure electrical connectivity, while allowing for easy separation and assembly of package components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor dies are connected and integrated within a package structure, then electrical connectivity and functionality are improved, but delamination stresses and reliability issues increase
Solution Approach 1:
The package structure is divided into multiple separate semiconductor dies that are individually processed and then integrated through wafer-level packaging. Each die remains as a distinct functional unit, allowing independent optimization and reducing stress concentration that would occur in monolithic structures.
Solution Approach 2:
Multiple semiconductor dies are stacked and integrated within a single package structure in a nested arrangement. The first and second semiconductor dies are positioned at different vertical levels, with interconnect structures bridging between them, creating a compact three-dimensional integration that improves electrical connectivity while managing mechanical stresses through the layered architecture.
2Productivity
If wafer-level packaging is used to process and package multiple dies, then manufacturing efficiency and productivity are improved, but process complexity and integration difficulty increase
Solution Approach 1:
Multiple semiconductor dies are processed and packaged simultaneously at the wafer level rather than individually. The first and second semiconductor dies undergo fabrication, testing, and packaging operations as integrated circuits on the same wafer substrate, consolidating multiple manufacturing steps into a unified process flow that dramatically improves productivity.
Solution Approach 2:
Semiconductor dies are processed, tested, and prepared for packaging while still on the wafer substrate before being separated and integrated into the final package structure. This preliminary processing and testing at the wafer level allows for early defect detection and ensures that only functional dies proceed to the integration stage, simplifying the overall manufacturing process.
Data Source
AI summary
A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.