PoP Semiconductor Package with Thick-Chip Wire-Bond Stacking
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Solution Overview
Problem
The challenge in developing semiconductor packages is to create a compact, multifunctional package-on-package (PoP) type semiconductor package that reduces volume while maintaining high bandwidth and reducing manufacturing costs, as existing solutions struggle to efficiently integrate multiple semiconductor chips with varying thicknesses and wire bonding configurations.
Innovation Solution
The semiconductor package incorporates a redistribution layer with redistribution line patterns and vias, a molding member surrounding the chips and bonding wires, and a specific stacking configuration of semiconductor chips with varying thicknesses, where the upper chip has a greater thickness than the lower chip, and bonding wires with uniform diameters that form a micro-pillar function to increase bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips with varying thicknesses are stacked in a PoP configuration, then the volume is reduced and integration is improved, but the manufacturing complexity and difficulty of aligning chips with different dimensions increases
Solution Approach 1:
The patent implements a package-on-package (PoP) configuration where multiple semiconductor chips are vertically stacked one on top of another. The lower chip serves as a base layer, and the upper chip is positioned directly above it, creating a nested three-dimensional structure. This nesting approach reduces the overall horizontal footprint while maintaining multiple functional layers, directly addressing the volume reduction goal while managing the complexity through standardized stacking procedures.
2Ease of manufacture
If bonding wires with uniform diameters are used to connect chips to redistribution layer, then the manufacturing cost is reduced and ease of manufacture is improved, but the bandwidth and signal transmission capability may be limited
Solution Approach 1:
The bonding wires in the patent serve multiple functions simultaneously. They provide electrical connection between the chip pads and redistribution layer, offer mechanical support for the upper chip, and function as a standardized interconnection medium that simplifies the manufacturing process. This multi-functionality allows uniform diameter wires to achieve both ease of manufacture and adequate bandwidth for the application.
3Stability of the object's composition
If a molding member surrounds all chips and bonding wires, then the structural stability and protection are improved, but the horizontal area occupied by the package increases
Solution Approach 1:
The patent transitions from a two-dimensional horizontal layout to a three-dimensional vertical stacking configuration. By positioning chips and bonding wires in the vertical dimension rather than spreading them horizontally, the molding member can enclose all components within a compact volume. This dimensional change allows the package to achieve structural stability through vertical integration while minimizing the horizontal footprint occupied by the external molding.
4Adaptability or versatility
If the upper semiconductor chip has greater thickness than the lower chip, then the functional integration and capacity are improved, but the difficulty of achieving coplanar surfaces for bonding increases
Solution Approach 1:
The patent applies different thicknesses to different chips in the stack based on their specific functional requirements. The upper chip is designed with greater thickness to accommodate additional functional layers or higher capacity devices, while the lower chip has a standard thickness suitable for its role as a base layer. This localized differentiation in thickness allows each chip to be optimized for its specific function while the overall stacking process manages the alignment challenges through controlled bonding procedures.
Data Source
AI summary
A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.