PoP Package Structure With Z-Interconnectors for Crack-Resistant Assembly
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Solution Overview
Problem
Conventional packaging processes for semiconductor chips face challenges in efficiently connecting and protecting delicate chips, especially with the increasing demand for more integrated functions and flexible package designs, where thermal stresses can cause cracks in solder bumps or solder balls.
Innovation Solution
The development of a package structure and method involving a carrier with a release layer, redistribution layers, Z-interconnectors, and a polymer region, where Z-interconnectors are formed with solder regions and reflowed to connect package components, and the carrier is released to form a Package-on-Package (PoP) structure, enhancing electrical performance and assembly yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging processes are used with flip-chip bonding, then semiconductor chips can be connected to package components, but thermal stresses cause cracks in solder bumps or solder balls
Solution Approach 1:
An underfill material is applied between the semiconductor chip and package substrate before final assembly to provide mechanical support and stress distribution, preventing thermal stress from concentrating on solder bumps and causing cracks
Solution Approach 2:
The underfill material acts as an intermediary substance between the chip and substrate, providing a compliant layer that absorbs and distributes thermal stresses, thereby protecting the solder joints from crack formation
2Adaptability or versatility
If Package-on-Package technology is used to expand integration ability, then more functions can be integrated and electrical performance improved, but package design and assembly complexity increases
Solution Approach 1:
The package system is divided into separate module layers (first package component, second package component) that can be independently fabricated and tested, then stacked together to form the complete PoP structure, reducing overall design complexity
Solution Approach 2:
Multiple package components are stacked in the vertical dimension rather than arranged horizontally, enabling higher integration density and improved electrical performance through shortened connecting paths while maintaining manageable design complexity through standardized stacking interfaces
3Productivity
If multiple duplicated semiconductor chips are fabricated on a single wafer, then production efficiency is improved, but the delicate chips require complex packaging to protect them
Solution Approach 1:
Multiple semiconductor chips are pre-fabricated on a single wafer in parallel, and the wafer-level processing allows for preliminary testing and preparation before singulation and final packaging, improving productivity while managing complexity through standardized processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical performance and reduces assembly complexity by shortening connecting paths and increasing yield through the use of redistribution layers, Z-interconnectors, and a polymer region, which helps in preventing cracks and ensuring stable connections.
Implementation Method 1
Z-interconnectors are formed with solder regions and reflowed to connect package components
Data Source
AI summary
A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.