Package-on-Package Redistribution Layout for Heat Dissipation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integration and efficient heat dissipation in package-on-package structures due to limitations in current three-dimensional integration technologies and redistribution layer designs.
Innovation Solution
A manufacturing method for a package-on-package structure involving a first redistribution layer with embedded conductive and dielectric layers, through insulator vias, and an insulating encapsulant, which improves heat dissipation and allows for versatile connections without additional processing steps, enabling better performance and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional integration technology is used for wafer level packaging, then integration density is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The package structure is divided into multiple separate packages (first package and second package) stacked vertically, with each package having its own redistribution layer and encapsulation structure. This segmentation allows heat to be dissipated from multiple surfaces and facilitates independent thermal management for each package, resolving the heat dissipation difficulty caused by high integration density.
Solution Approach 2:
The invention transitions from planar two-dimensional packaging to three-dimensional vertical stacking of multiple packages. By utilizing the vertical dimension, the package structure achieves high integration density while maintaining heat dissipation pathways through the vertical arrangement and separate encapsulation structures that allow thermal management in the third dimension.
2Ease of manufacture
If conventional redistribution layer design is used, then manufacturing is simpler, but heat dissipation and connection versatility are limited
Solution Approach 1:
The redistribution layer is designed with exposed connecting portions that can be coplanar with the dielectric layer surface, enabling the same structure to serve multiple functions: electrical connection, mechanical support, and thermal management. This universal design allows versatile connections between stacked packages without requiring additional specialized processing steps, achieving both manufacturing simplicity and connection versatility.
3Reliability
If additional processing steps are added to improve heat dissipation and connections, then performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention combines multiple functions into existing structures: the redistribution layer serves both electrical connection and thermal management functions, the encapsulation structure provides both protection and heat dissipation pathways, and the exposed connecting portions enable both mechanical alignment and electrical connection. By merging these functions into existing structures rather than adding separate processing steps, performance is improved without significantly increasing manufacturing complexity or cost.
Data Source
AI summary
A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.