Package-on-Package Semiconductor Structure with Edge-Concentrated Chip Pads

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Solution Overview

Problem

Semiconductor packages face challenges in reducing overall thickness and simplifying design complexity, particularly in achieving high memory capacity and bandwidth with efficient data processing while maintaining high-speed operation.

Innovation Solution

The semiconductor package employs a package-on-package (POP) structure with a first and second substrate, each containing semiconductor chips with chip pads arranged on opposite edges for 32-bit channels, connected via through silicon vias (TSVs) and flip-chip bonding, allowing for simplified wiring connections and reduced thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If chip pads are concentrated on one edge of the semiconductor chip, then wiring connection is simplified, but the chip cannot support multiple channels efficiently

Engineering Contradiction:
Improvewiring connection complexityVSAvoiddata processing capacity
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The chip pads are segmented and distributed to different edges of the semiconductor chip according to channel groups. Specifically, first chip pads corresponding to first channel groups are located at a first edge, while second chip pads corresponding to second channel groups are located at a second edge opposite to the first edge. This segmentation allows multiple channels to be supported while maintaining simplified wiring connections for each channel group.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multiple semiconductor chips are stacked to increase memory capacity, then memory capacity is improved, but overall package thickness increases

Engineering Contradiction:
Improvememory capacityVSAvoidpackage thickness
Core Design Contradiction:
Quantity of substanceVSLength of stationary object

Solution Approach 1:

The patent utilizes three-dimensional stacking in the vertical dimension while optimizing the horizontal dimension through edge-based pad distribution. Multiple semiconductor chips are stacked vertically, with connection members extending through the stack. The edge-based pad concentration allows for more efficient horizontal wiring, enabling higher density stacking and thus increasing memory capacity without proportionally increasing package thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If through silicon vias are used to connect stacked chips, then vertical interconnection is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvevertical interconnectionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The through silicon vias are formed as preliminary structures before the semiconductor chips are mounted and connected. The connection members extend through the stacked chips, establishing vertical interconnection pathways in advance. This preliminary formation of via structures simplifies the overall manufacturing process by separating the via formation step from the chip stacking and bonding steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances memory capacity, reduces substrate thickness, and simplifies wiring connections, thereby improving data processing efficiency and operational speed.

Implementation Method 1

connected via through silicon vias (TSVs)

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

flip-chip bonding

Methodology Applied
Scientific EffectBonding: Welding

Data Source

PatentUS8791559B2Semiconductor package with package on package structure
Publication Date: 2014.07.29 SAMSUNG ELECTRONICS CO LTD
  • US8791559B2 patent drawing
  • US8791559B2 patent drawing
  • US8791559B2 patent drawing

AI summary

A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.