Package on Package Semiconductor Assembly Inductance Reduction
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Solution Overview
Problem
In high integration semiconductor packages, parasitic inductance components in the wiring path between passive elements and semiconductor chips cause noise and logical defects, limiting the efficiency of data processing in compact electronic devices.
Innovation Solution
A semiconductor assembly with a package on package (POP) structure is designed, where a decoupling capacitor is strategically placed close to the semiconductor chip within the POP structure, minimizing inductance components by being disposed in either the first or second semiconductor package and electrically connected to the second semiconductor chip, thereby reducing resistance and inductance in the wiring path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive elements are placed far from semiconductor chips in POP structure, then easier manufacturing and assembly, but parasitic inductance increases causing noise and logical defects
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional vertical stacking in POP structure, enabling passive elements to be positioned in multiple spatial dimensions relative to semiconductor chips. This dimensional change allows optimization of electrical performance by placing passive elements on different layers (first upper substrate or second lower substrate) while maintaining manufacturability through standardized vertical assembly processes
Solution Approach 2:
The patent applies different placement strategies for different passive elements based on their electrical characteristics and connection requirements. Specific passive elements are selectively positioned on the first upper substrate or second lower substrate depending on their function, allowing localized optimization of inductance reduction while maintaining overall assembly ease
2Object-affected harmful factors
If passive elements are placed close to semiconductor chips, then parasitic inductance is minimized reducing noise, but device complexity increases
Solution Approach 1:
The patent implements nesting by placing passive elements within the vertical stack of the POP structure, specifically on the first upper substrate or second lower substrate that are already part of the package assembly. This nested arrangement allows passive elements to be integrated into the existing package layers without requiring separate mounting operations, thereby reducing inductance while controlling complexity through hierarchical integration
3Area of stationary object
If POP structure is used for high integration, then space efficiency increases, but wiring path inductance increases causing noise
Solution Approach 1:
The patent utilizes vertical dimension in POP structure to reduce horizontal wiring distances. By positioning passive elements on adjacent layers (first upper substrate or second lower substrate) vertically close to semiconductor chips, the wiring paths transition from long planar traces to short vertical connections through bumps and vias, significantly reducing inductance while maintaining compact footprint
Solution Approach 2:
The patent optimizes local wiring paths by selectively positioning passive elements on specific substrates (first upper or second lower) based on their electrical connection requirements. This localized optimization ensures that critical power and signal paths have minimal inductance while other areas maintain the benefits of high-density vertical integration
Data Source
AI summary
A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.