Package-on-Package Semiconductor Stacking with Matching Substrates

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Solution Overview

Problem

Existing package-on-package (POP) semiconductor technologies face challenges in achieving high capacity and compactness while maintaining reliability, often resulting in low yield due to thermal expansion coefficient differences and complex stacking processes.

Innovation Solution

A POP semiconductor package design that includes a first and second substrate with semiconductor chips, connected by an internal connection member, where the substrates have matching thermal expansion coefficients and a reduced internal connection terminal size to minimize warping and enhance reliability, allowing for high-capacity stacking with improved electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor chips are vertically stacked to achieve high density, then capacity and compactness are improved, but reliability decreases due to thermal expansion coefficient differences

Engineering Contradiction:
Improvechip stacking densityVSAvoidpackage yield
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the material parameter of the substrates by selecting materials with matching thermal expansion coefficients. This parameter change eliminates the thermal expansion mismatch that causes warping and reliability issues in multi-chip stacked packages, thereby improving package yield while maintaining high stacking density.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material selection where the first and second substrates are made from materials specifically chosen to have compatible thermal expansion properties. This composite approach ensures that when chips are stacked vertically, the entire package structure expands and contracts uniformly during thermal cycling, preventing internal stress and warping.

Inventive Principle:
Principle #40Composite materials

2Reliability

If internal connection terminal size is reduced to minimize warping, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvewarping preventionVSAvoidconnection terminal design
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the dimensional parameter of the internal connection terminals by reducing their size. This size reduction minimizes the thermal mass and stress concentration points, thereby preventing warping in the stacked package. The smaller terminals also reduce the number of materials and processing steps required, simplifying manufacturing despite the precision requirements.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables a low-height, high-capacity POP semiconductor package with improved reliability by minimizing thermal expansion issues and optimizing the internal connection process, preventing warping and ensuring efficient electrical connections between stacked packages.

Implementation Method 1

The internal connection member may be between the first back side and the second back side and may electrically connect the first package to the second package

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

The first substrate may have a thermal expansion coefficient equal or similar to that of the second substrate

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8169066B2Semiconductor package
Publication Date: 2012.05.01 SAMSUNG ELECTRONICS CO LTD
  • US8169066B2 patent drawing
  • US8169066B2 patent drawing
  • US8169066B2 patent drawing

AI summary

Provided is a semiconductor package including a first package and a second package. The first package includes a first substrate having a first front side and a first back side opposing the first front side. The first package further includes a first semiconductor chip on the first front side and an external connection member on the first semiconductor chip. The external connection member may be configured to electrically connect the first semiconductor chip to an external device. The second package includes a second substrate having a second back side facing the first back side of the first substrate and a second front surface opposing the second back side. The second package includes a second semiconductor chip on the second front side. The semiconductor package further includes an internal connection member between the first back side and the second back side to electrically connect the first package to the second package.