Package-on-Package Semiconductor Stacking with TSVs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor package technologies face challenges in enhancing integration and diversifying functions while maintaining a lightweight and efficient manufacturing process for package on package (POP) type semiconductor devices.
Innovation Solution
A semiconductor package design incorporating a first and second semiconductor package stacked with through silicon vias (TSVs) for electrical connectivity, internal sealants for chip stacking, and package-connecting members to reduce overall height and enhance integration, featuring a flip-chip type configuration with exposed sealants and TSVs for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked to enhance integration and diversify functions, then the degree of integration and functionality are improved, but the height of the package increases
Solution Approach 1:
The patent implements a package-on-package (POP) structure where a first semiconductor package is stacked on a second semiconductor package, with each package containing multiple semiconductor chips. This nested arrangement allows multiple functional units to be integrated vertically while maintaining a compact overall height by optimizing the stacking configuration and using through-silicon via (TSV) technology for electrical interconnection between layers.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional vertical stacking, utilizing the height dimension for chip integration. By stacking chips and packages in the vertical direction and using TSVs for through-layer electrical connections, the design achieves high integration without excessive height increase, effectively utilizing spatial dimensions.
2Reliability
If through silicon vias (TSVs) are used for electrical connectivity between stacked chips, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the electrical connection path into segmented TSV structures that pass through individual chips and packages. Each TSV is formed as a separate conductive via through the silicon substrate, allowing independent formation and testing of connection paths. This segmentation enables reliable electrical interconnection while facilitating modular manufacturing processes.
Solution Approach 2:
The patent uses TSVs as intermediary conductive structures that mediate electrical connection between stacked semiconductor chips and packages. The TSVs serve as vertical interconnectors that bridge different packaging layers, enabling signal and power transmission through the three-dimensional structure without requiring complex external wiring.
3Stability of the object's composition
If internal sealant is used to fill space between stacked chips, then structural stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies internal sealant to fill spaces between stacked semiconductor chips and packages before final assembly and bonding. This preliminary sealing action prevents misalignment and ensures proper positioning of chips during the stacking process, thereby maintaining structural stability while reducing the stringency of manufacturing precision requirements.
Solution Approach 2:
The internal sealant functions as a disposable filling material that is applied in excess and then trimmed or cured to achieve the final precise configuration. This approach allows for easier assembly with lower precision requirements during manufacturing, as the sealant can be adjusted or removed if needed, rather than requiring perfect initial positioning.
Data Source
AI summary
A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.