PoP Solder Ball Placement for Size Reduction
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Solution Overview
Problem
The challenge in packaging semiconductor chips for portable devices is to reduce the size and height of package on packages (PoP) to save space on system boards, particularly in smartphones and tablets, while ensuring efficient electrical connectivity and signal transmission between stacked packages.
Innovation Solution
The implementation of a package on package configuration where stack connection solder balls are formed only around two sides facing each other, connecting a bottom package with a first chip die and a second chip die to a top package containing a third chip die, using flip-chip structures and underfill materials, with all signals and supply voltages transmitted through specific solder balls to minimize package size and height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stack connection solder balls are disposed around all four sides of the bottom package, then connection reliability is improved, but package size and height increase
Solution Approach 1:
The patent extracts the stack connection solder balls from a complete four-sided arrangement and repositions them to only two opposite sides of the bottom package. This selective removal and repositioning maintains sufficient connection reliability while significantly reducing the package footprint and height, directly resolving the contradiction between connection reliability and package size.
Solution Approach 2:
The patent introduces asymmetry in the solder ball distribution by placing stack connection solder balls on only two opposite sides rather than symmetrically on all four sides. This asymmetric configuration optimizes space utilization and reduces package dimensions while preserving essential electrical connections between the bottom and top packages.
2Reliability
If multiple stack connection solder balls are used to connect bottom and top packages, then electrical connection reliability is improved, but surface area requirement increases
Solution Approach 1:
The patent extracts unnecessary solder balls from the connection arrangement, retaining only the essential two-sided configuration. This reduces the total surface area occupied by solder balls while maintaining adequate electrical connection reliability through the remaining strategically positioned connection points.
Solution Approach 2:
The patent transitions from a two-dimensional surface distribution of solder balls around all four sides to a more compact arrangement concentrated on two opposite sides. This dimensional optimization reduces the required surface area while preserving vertical connection integrity between packages.
3Area of stationary object
If package on package structure is implemented to reduce PCB surface area, then device miniaturization is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent simplifies the PoP structure by extracting unnecessary complexity from the solder ball arrangement, reducing it to a two-sided configuration. This simplification eases manufacturing requirements while maintaining the space-saving benefits of the PoP architecture, thereby reducing PCB surface area without excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the size and height of PoP, enabling efficient electrical connectivity and signal transmission, thereby supporting the development of smaller, lighter portable electronic devices.
Implementation Method 1
first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB
Implementation Method 2
An empty space between the first chip die and the first PCB and an empty space between the second chip die and the first PCB may be filled with a capillary underfill (CUF) material
Implementation Method 3
An empty space between the first chip die and the first PCB, and an empty space between the second chip die and the first PCB, the first chip die, and the second chip die may be encapsulated using a molded underfill (MUF) material
Data Source
AI summary
A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.