Pop Stack Absolute Instruction in Run-to-Completion Processor
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Solution Overview
Problem
Conventional pipelined processors require substantial integrated circuit area due to the presence of an instruction counter and associated control circuitry, limiting their compact implementation and efficiency.
Innovation Solution
A pipelined run-to-completion processor design that omits the instruction counter, initiating instruction fetching only through external input data or initial fetch information, allowing for a compact implementation of approximately ten thousand equivalent gates, and incorporating a lookup table circuit to determine memory addresses and execute modular code across multiple tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an instruction counter and associated control circuitry are included in a pipelined processor, then the processor can automatically track and fetch instructions sequentially, but the integrated circuit area increases substantially
Solution Approach 1:
The patent removes the instruction counter and its associated control circuitry from the processor architecture. Instead of automatic sequential tracking, the system uses external input data values and initial fetch information to trigger instruction fetching, thereby eliminating the hardware components that consume significant circuit area while achieving the same functional outcome through a different mechanism
Solution Approach 2:
The system uses the input data values themselves and their associated metadata to drive the instruction fetching process. The input data serves dual purposes: as the actual data to be processed and as the trigger mechanism for fetching the appropriate instruction block, eliminating the need for separate control circuitry
2Adaptability or versatility
If a lookup table circuit is used to convert table number values into base address values, then code execution can jump between sections and tables flexibly, but the circuit complexity increases
Solution Approach 1:
The lookup table circuit is pre-populated with base address values for multiple code tables during system initialization or manufacturing. This allows the circuit to perform simple table lookups during execution without requiring complex address calculation logic, achieving flexible code execution while maintaining relatively simple circuitry
Solution Approach 2:
The lookup table circuit acts as an intermediary between the input data values and the external memory system. It converts table number values from the input data into base address values that can be used to fetch instruction blocks from the appropriate locations in external memory, simplifying the overall address translation process
Data Source
AI summary
A pipelined run-to-completion processor executes a pop stack absolute instruction. The instruction includes an opcode, an absolute pointer value, a flag don't touch bit, and predicate bits. If a condition indicated by the predicate bits is not true, then the opcode operation is not performed. If the condition is true, then the stack of the processor is popped thereby generating an operand A. The absolute pointer value is used to identify a particular register of the stack, and the content of that particular register is an operand B. The arithmetic logic operation specified by the opcode is performed using operand A and operand B thereby generating a result, and the content of the particular register is replaced with the result. If the flag don't touch bit is set to a particular value, then the flag bits (carry flag and zero flag) are not affected by the instruction execution.