Package-on-Package Stack Reducing Thickness via Interposer Bonding
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Solution Overview
Problem
The challenge is to increase the number of semiconductor chips in a limited space without increasing the overall thickness of electronic products, as current technologies face limitations in manufacturing high-capacity semiconductor chips and stacking multiple chips effectively.
Innovation Solution
A package-on-package type stack package is developed, comprising a bottom package with an interposer, bond fingers, and a first semiconductor chip, and a top package with a second semiconductor chip, where both packages are electrically coupled through bonding wires and encapsulation members, allowing for the insertion of connection members into via holes to reduce overall thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to increase capacity, then the number of chips per package increases, but the overall thickness of the package increases
Solution Approach 1:
The patent implements package-on-package stacking where a top package is mounted on a bottom package, with each package containing semiconductor chips. This nested arrangement allows multiple chips to be integrated vertically while maintaining a compact profile by utilizing the interposer structure and optimized connection methods between packages.
Solution Approach 2:
The patent introduces an interposer structure with electrodes arranged along edges, which serves as an intermediary between the top and bottom packages. This interposer enables electrical coupling through bonding wires and facilitates the stacking architecture, allowing increased chip capacity while managing the thickness through its specific electrode arrangement and bonding configuration.
2Quantity of substance
If more semiconductor chips are mounted in a limited space, then chip capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor system into separate packages (top package and bottom package), each containing its own semiconductor chips. This segmentation allows for independent manufacturing and testing of each package before stacking, simplifying the overall manufacturing process while enabling high chip capacity through the modular package-on-package architecture.
Solution Approach 2:
The interposer structure serves multiple functions: it provides electrical coupling between packages, supports the stacking architecture, and enables signal transmission through its electrode arrangement. This multi-functional design reduces the need for additional specialized components, thereby managing manufacturing complexity while achieving high chip integration.
3Reliability
If packages are stacked to increase chip capacity, then electrical characteristics improve, but package thickness increases
Solution Approach 1:
The patent optimizes the electrical characteristics of the stacked package by controlling parameters such as the arrangement of electrodes along the edges of the interposer, the configuration of bonding wires, and the positioning of bond fingers. These parameter optimizations enable improved electrical performance while maintaining a reduced package thickness through efficient signal routing and minimized connection lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a low-profile package-on-package type stack package with reduced overall thickness, facilitating the integration of more semiconductor chips in a compact form, enhancing electrical characteristics and functionality without increasing the package thickness.
Implementation Method 1
first bonding wires electrically coupling the first bonding pads and the electrodes. The bottom package also includes second bonding wires electrically coupling the electrodes and the first bond fingers
Implementation Method 2
forming the first connection members in the respective via holes to be electrically coupled with the second bonding wires
Implementation Method 3
a first encapsulation member formed to cover the first bond fingers, the upper surfaces and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires
Data Source
AI summary
A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.