Package-on-Package Substrate Layout for Warpage-Resistant Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving increased storage capacity, reduced thickness, and improved structural and electrical connection reliability, particularly in package on package type configurations.
Innovation Solution
A semiconductor package design featuring a first and second package substrate with core structures and solder balls, strip guides, and a molding layer, arranged to maintain structural integrity and enhance electrical connections through specific dimensional alignments and symmetrical row arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If core structures and solder balls are arranged between package substrates to increase storage capacity, then storage capacity is improved, but warpage and structural reliability deteriorate
Solution Approach 1:
The patent applies asymmetry by positioning core structures and solder balls at different distances from the semiconductor chip in different dimension directions. Specifically, a first portion of core structures and solder balls are located at a first distance in a first dimension direction, while a second portion are located at a second distance in a second dimension direction, creating an asymmetric distribution pattern that balances warpage forces while maintaining high storage capacity
Solution Approach 2:
The patent transitions from two-dimensional array arrangements to three-dimensional spatial distribution by utilizing multiple dimension directions (first dimension direction and second dimension direction) for positioning core structures and solder balls. This multi-dimensional arrangement allows optimization of both storage capacity and warpage control simultaneously
2Adaptability or versatility
If more core structures and solder balls are added to increase functionality, then device complexity increases, but manufacturing precision requirements worsen
Solution Approach 1:
The patent segments the arrangement of core structures and solder balls into distinct groups based on their dimensional positions. By dividing them into a first portion (in first dimension direction) and a second portion (in second dimension direction), the patent simplifies the manufacturing process while maintaining high functionality, as each segment can be positioned and controlled independently with standard precision
3Length of stationary object
If package substrates are arranged in package on package configuration to reduce thickness, then package thickness is reduced, but electrical connection reliability deteriorates
Solution Approach 1:
The patent introduces semiconductor chips as intermediary elements between the lower package substrate and upper package substrate. The chips are electrically connected to both substrates through bump electrodes and pad electrodes, creating reliable electrical connection paths that span across the thin package structure, thus maintaining electrical connection reliability while achieving reduced thickness
Data Source
AI summary
A semiconductor package includes a first package substrate, a semiconductor chip on the first package substrate, a second package substrate over the first package substrate and the semiconductor chip, and a plurality of core structures and a plurality of solder balls. The core structures and the solder balls are between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a second dimension direction that is different than the first dimension direction. The semiconductor package includes a plurality of strip guides between the semiconductor chip and the plurality of core structures, and in parallel with a periphery of the semiconductor chip.