PoP Stacked-Chip Test Device for Bottom Chip Failure Identification
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Solution Overview
Problem
Current manual testing methods for package-on-package (PoP) stacked-chips are inefficient in identifying the source of low yields or errors, as they require individual placement and testing of top and bottom chips, making it difficult to differentiate between the two in case of test failures.
Innovation Solution
A test device with a test head containing a top chip and equipped with test contacts or probes that electrically connect to the bottom chip's soldering points, allowing for automated testing and differentiation between top and bottom chip failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual testing methods are used for PoP stacked-chips, then individual chip placement and testing can be performed, but it becomes difficult to differentiate between top chip and bottom chip failures
Solution Approach 1:
The patent applies segmentation by separating the testing process into two distinct modes: a first testing mode that tests only the bottom chip, and a second testing mode that tests both chips. This segmentation allows precise identification of failure sources by comparing test results from different modes, directly resolving the contradiction between measurement precision and device complexity.
2Productivity
If individual manual placement of top chip onto bottom chip is performed, then stacking integration can be achieved, but testing efficiency and throughput are reduced
Solution Approach 1:
The patent implements self-service by designing a test head that automatically holds the top chip and performs testing operations without requiring manual intervention for chip placement. The test head integrates both chips and performs self-contained testing, eliminating the need for external manual placement operations and significantly improving testing throughput.
3Reliability
If conventional stacked-chip packaging is used, then final test yield can be assessed, but problem source identification becomes complicated when low yields or continuous errors occur
Solution Approach 1:
The patent applies preliminary action by performing a bottom chip-specific test before final packaging and stacking. This preliminary testing step identifies and eliminates defective bottom chips in advance, ensuring that only qualified bottom chips proceed to final assembly. This prevents wasted effort on faulty components and simplifies problem source identification by ruling out bottom chip failures beforehand.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The test device improves the yield and cost-effectiveness of PoP stacked-chips by enabling efficient identification and elimination of failed bottom chips before packaging, and enhances throughput through automated testing and vacuum absorption capabilities.
Implementation Method 1
The nozzle is installed about the center of the lower surface of the test head, for vacuum absorbing the bottom chip
Implementation Method 2
The air flow passage penetrates the test head and connecting the nozzle, for exhausting the air flow so as to generate the absorbing force
Data Source
AI summary
A test device is provided for testing a bottom chip of a package-on-package (PoP) stacked-chip. An upper surface of the bottom chip has a plurality of soldering points for electrically connecting a plurality of corresponding soldering points of a top chip of the PoP stacked-chip. The test device includes a test head and a plurality of test contacts. The test head has the top chip installed inside. The plurality of test contacts is installed on a lower surface of the test head and electrically connected to the plurality of corresponding soldering points of the top chip inside the test head. When the lower surface of the test head contacts the upper surface of the bottom chip, the plurality of test contacts is electrically connected to the plurality of soldering points for testing the bottom chip.