Package-on-Package Test Routing for Reliable Redistribution Layers
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Solution Overview
Problem
Current semiconductor packages lack high electrical reliability and efficient testing capabilities, particularly in package-on-package configurations, where the integration of multiple semiconductor devices with different functions is challenging due to limited test sensitivity and inadequate redistribution layer connectivity.
Innovation Solution
A semiconductor package design featuring a redistribution layer with conductive lines, vias, and pads connected to external terminals, along with a testable electrical path that includes multiple external connection terminals for input and output signals, enabling comprehensive testing of the package's electrical paths and improving connectivity between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor package structures are used, then manufacturing simplicity is maintained, but electrical reliability and testing sensitivity are insufficient
Solution Approach 1:
The package structure is divided into distinct functional layers: lower redistribution layer with test paths, semiconductor chip, upper redistribution layer, and connection structures. This segmentation allows independent optimization of each layer for reliability while maintaining overall manufacturing feasibility through standardized assembly processes.
Solution Approach 2:
Connection structures (solder bumps, conductive pillars, or wire bonds) serve as intermediary elements between the lower and upper redistribution layers. These intermediaries provide reliable electrical connection and mechanical bonding, enhancing overall package reliability while allowing modular manufacturing approaches.
2Measurement precision
If conventional testing methods are used, then manufacturing simplicity is maintained, but testing sensitivity and coverage are insufficient
Solution Approach 1:
Test paths are pre-configured within the lower redistribution layer during manufacturing, with test signal input terminals and output terminals positioned on the package exterior. This preliminary arrangement enables comprehensive testing of conductive lines and vias before final package assembly, improving detection sensitivity without requiring complex post-assembly test fixtures.
Solution Approach 2:
The lower redistribution layer serves dual functions: it redistributes electrical signals to the semiconductor chip and simultaneously provides integrated test paths for quality verification. This multi-functionality eliminates the need for separate test structures, maintaining manufacturing simplicity while achieving comprehensive testing coverage.
3Adaptability or versatility
If package-on-package configuration is implemented, then multifunctionality and integration are improved, but electrical reliability and connectivity between layers become challenging
Solution Approach 1:
Connection structures act as reliable intermediaries between lower and upper packages, providing both mechanical support and electrical connectivity. These structures ensure stable signal transmission across package interfaces, maintaining high reliability in package-on-package configurations while enabling multifunctional integration.
Solution Approach 2:
The patent transitions from planar two-dimensional routing to three-dimensional vertical stacking with multiple redistribution layers. This dimensional change enables higher integration density and multifunctionality while the lower redistribution layer maintains comprehensive test access to all conductive paths, ensuring reliability in the vertical architecture.
Data Source
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AI summary
A semiconductor package (1) includes: a redistribution layer (100) including a plurality of conductive lines (126), a plurality of conductive vias (128) each connected to at least one of the plurality of conductive lines (126), and a plurality of lower pads (122) each connected to one of the plurality of conductive vias (128); a semiconductor chip (10) on the redistribution layer (100); and a plurality of external connection terminals (150) attached to the plurality of lower pads (122); and a plurality of electrical paths, wherein each of the plurality of electrical paths includes at least one of the plurality of conductive lines (126) and at least one of the plurality of conductive vias (128). The plurality of electrical paths is configured for testing the plurality of conductive lines and the plurality of conductive vias (128) and is connected to at least four of the external connection test terminals (152, 154).