Testing Conductive Pad Placement in POP Semiconductor Substrates
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Solution Overview
Problem
The Package on Package (POP) semiconductor structure faces challenges in miniaturization, high-performance, reliability, and manufacturing cost due to warping caused by thermal expansion differences between wiring and insulating layers, and difficulties in routing wires with reduced pitch and staggered pad arrangements.
Innovation Solution
The POP structure is designed with the testing conductive pads arranged outside the external input/output conductive pads on the first wiring substrate, allowing for reduced wiring density and improved rigidity by using conductive pads in the outer row for coupling, which reduces the number of wirings and minimizes warping, and enables the use of less expensive materials by allowing for narrower pitch conductive pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of signal wirings is increased to accommodate more input/output terminals, then the system performance is improved, but the wiring substrate becomes more prone to warping due to thermal expansion differences
Solution Approach 1:
The patent transitions from a planar SIP architecture to a three-dimensional POP architecture by stacking multiple wiring substrates vertically. This spatial reorganization allows signal terminals to be distributed across different layers and positions, increasing the total number of I/O terminals without concentrating all wirings in a single plane, thereby reducing thermal expansion-induced warping in any one substrate.
2Volume of moving object
If the pitch of conductive pads is reduced to increase wiring density, then the device size is minimized, but the manufacturing precision requirements increase
Solution Approach 1:
The patent divides the conductive pads into two distinct groups: external input/output signal pads and inspection pads. This segmentation allows each group to be optimized independently - the external pads can use wider spacing suitable for solder ball attachment, while the inspection pads can be positioned at convenient locations for testing, thereby reducing the overall pitch requirement and easing manufacturing precision demands.
3Area of stationary object
If testing conductive pads are placed inside the external input/output conductive pads, then the substrate area is utilized efficiently, but the wire routing becomes more complex
Solution Approach 1:
The patent extracts the inspection pads from the internal region and positions them outside the external input/output conductive pads. This separation simplifies wire routing by allowing independent access to inspection pads without interfering with the solder ball attachment process for external pads, while still achieving efficient substrate area utilization through strategic peripheral placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration promotes miniaturization and high-performance, enhances reliability by reducing thermal expansion-induced warping, and lowers manufacturing costs by simplifying wire routing and using less expensive substrate materials.
Implementation Method 1
signal wirings that couple the terminals of the plurality of chips and the external input/output signal terminals
Implementation Method 2
an external input/output signal terminal including a solder ball etc. is coupled onto the pad
Implementation Method 3
a multilayer wiring substrate having an insulating layer and a wiring layer
Data Source
AI summary
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.