PoP Structure With Thick Logic Die and Copper-Cored Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current package-on-package (PoP) solutions in semiconductor packaging face challenges in improving reliability and durability, particularly in high-end devices that require higher I/O and performance, where the stacked structure's effectiveness is limited by the thickness and electrical connectivity of logic dies and integrated circuit devices.
Innovation Solution
A package-on-package design featuring a first package with a thick logic die mounted on a bottom substrate in a flip-chip configuration, electrically connected via conductive elements, and a second package stacked on top, using copper cored solder balls to bridge the substrates with a sealing resin filling the gap, enhancing electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick logic die is used in PoP packaging, then reliability and durability are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the PoP package into distinct functional layers: bottom substrate with thick logic die, gap region with sealing resin, and top substrate. This segmentation allows each component to be optimized independently while maintaining overall reliability.
Solution Approach 2:
The patent introduces a sealing resin as an intermediary material filling the gap between the bottom and top substrates. This mediator provides mechanical support, electrical insulation, and stress distribution, enabling the use of thick logic dies without compromising package integrity.
2Reliability
If copper cored solder balls are used to electrically connect substrates, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs copper cored solder balls as a composite material combining the high electrical conductivity of copper with the solderability and ductility of solder alloy. This composite structure enhances electrical connectivity while providing tolerance for manufacturing variations through the ductile solder outer layer.
3Strength
If sealing resin is used to fill the gap between substrates, then structural integrity is improved, but volume of the package increases
Solution Approach 1:
The patent utilizes sealing resin as a flexible encapsulating material that conforms to the gap geometry between substrates. This thin-film approach provides comprehensive structural support and protection while minimizing the volume increase, as the resin fills only the necessary gap space rather than adding substantial external volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and durability of semiconductor packages by ensuring robust electrical connections and improved communication between logic dies and integrated circuit devices, supporting higher performance and I/O requirements in high-end devices.
Implementation Method 1
a plurality of copper cored solder balls disposed between the bottom substrate and the top substrate around the logic die and the at least one integrated circuit device to electrically connect the bottom substrate with the top substrate
Implementation Method 2
a sealing resin filling in the gap between the bottom substrate and the top substrate and sealing the logic die, the at least one integrated circuit device, and the plurality of copper cored solder balls in the gap
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A package-on-package (3) includes a first package (10) and a second package (20) on the first package (10). The first package (10) includes a bottom substrate (100) and a top substrate (300) space apart from the bottom substrate (100) such that the bottom substrate (100) and the top substrate (300) define a gap therebetween. A logic die (50) and an IC device (80) are mounted on the bottom substrate (100) in a side-by-side configuration. The logic die (50) has a thickness not less than 125 micrometers. Copper cored solder balls (60) are disposed between the bottom substrate (100) and the top substrate (300) around the logic die (50) and the IC device (80) to electrically connect the bottom substrate (100) with the top substrate (300). A sealing resin (SM) is filled into the gap between the bottom substrate (100) and the top substrate (300) and seals the logic die (50), the IC device (80), and the copper cored solder balls (60) in the gap.