Package-on-Package Semiconductor Stacking via Through Electrodes
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Solution Overview
Problem
Package-on-package (POP) semiconductor technologies face challenges with yield reduction and restricted chip selection, leading to inefficiencies in high-density chip stacking and compact electronic device design.
Innovation Solution
The implementation of semiconductor packages with through electrodes that directly connect a package substrate and semiconductor chip without micro-bumps, allowing for a narrower pitch to expand to a wider pitch without interposers, enabling vertical stacking and electrical connection between upper and lower packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-chip stack package is used to achieve high density chip stacking, then chip integration density is improved, but yield is reduced
Solution Approach 1:
The package is divided into a lower package and an upper package that can be independently fabricated and tested before stacking. This segmentation allows each package to be separately evaluated for quality, ensuring only known good packages are stacked, thereby maintaining high yield while achieving high chip integration density through vertical stacking.
2Reliability
If POP technology is used to reduce yield reduction, then reliability is improved, but chip selection is restricted
Solution Approach 1:
The lower package substrate is designed with a universal mounting structure that can accommodate different types of semiconductor chips (e.g., logic chips, memory chips, sensors). This universal design allows various chip types to be mounted on the same lower package substrate, which is then stacked with an upper package substrate, thereby maintaining POP technology's yield benefits while expanding chip selection flexibility.
3Reliability
If connection terminals are provided between upper and lower packages, then electrical connection is improved, but package complexity is increased
Solution Approach 1:
The connection terminals are integrated directly into the package substrates themselves, merging the electrical connection function with the structural substrate. This eliminates the need for separate, complex interconnection structures between packages, thereby improving electrical connection reliability while minimizing the increase in overall package complexity.
Data Source
AI summary
A semiconductor package includes a lower package with a lower semiconductor chip on a lower package substrate, and an upper package with an upper semiconductor chip on an upper package substrate. The upper semiconductor chip has a plurality of chip pads and the upper package substrate has a plurality of substrate pads. The upper package is stacked on the lower package. The chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch. The upper package substrate has a plurality of connection lines that electrically connect the substrate pads to the chip pads.