Semiconductor Package Through-Via Structure for Fine-Pitch PoP Routing
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Solution Overview
Problem
The challenge in semiconductor packaging is to reduce the mounting area while maintaining high performance, particularly in package-on-package structures, where existing technologies face limitations in designing redistribution layers and through-vias for vertical electrical connections.
Innovation Solution
A semiconductor package design that includes a first redistribution structure with a first insulating layer and redistribution layer, a semiconductor chip with buried connection terminals, an encapsulant, a second redistribution structure, and a through-via with a pattern portion buried in the insulating layer and a via portion extending through the encapsulant, allowing for a high degree of freedom in designing the redistribution layer and reducing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through-via is formed to provide vertical electrical connection in a package-on-package structure, then electrical connectivity is improved, but congestion in the redistribution layer increases
Solution Approach 1:
The patent applies dimensionality change by forming the pattern portion at a different height level within the insulating layer rather than at the same level as the connection terminal. This vertical separation in the insulating layer creates additional spatial dimension for routing, allowing the redistribution layer to connect to both the connection terminal and the through-via pattern portion without congestion, while maintaining proper electrical connectivity through the via structure.
2Area of stationary object
If the mounting area is reduced for miniaturization, then product size is improved, but design freedom for redistribution layer is reduced
Solution Approach 1:
The patent utilizes the vertical dimension within the insulating layer by positioning the pattern portion at a different height than the connection terminal. This allows the redistribution layer to access both elements without requiring additional lateral space, thereby maintaining design freedom and routing flexibility while achieving miniaturization of the mounting area.
3Reliability
If the pattern portion height is increased to improve electrical connection, then connectivity is improved, but overall package thickness increases
Solution Approach 1:
The patent applies preliminary action by forming the pattern portion within the insulating layer at a strategically positioned height before final encapsulation. This allows the redistribution layer to make optimal electrical connection to both the connection terminal and the through-via pattern portion during the manufacturing process, ensuring reliable connectivity while maintaining control over the final package thickness through precise layer positioning.
Data Source
AI summary
A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.