POP Semiconductor Package Underfill Layout for Joint Crack Prevention

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Solution Overview

Problem

In semiconductor packaging, joint cracks in conductive connection members due to thermal stress reduce board-level reliability and heat dissipation efficiency in package-on-package (POP) devices.

Innovation Solution

A semiconductor package design featuring an underfill member between the lower and upper packages, with an asymmetric arrangement of the upper package to create an underfill region, which prevents joint cracks and enhances heat dissipation by filling the space between the packages and serving as a heat dissipation path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an upper package is stacked on a lower package using conductive connection members in a POP device, then functionality and miniaturization are improved, but joint cracks occur due to thermal stress, reducing board-level reliability

Engineering Contradiction:
Improvefunctionality and miniaturizationVSAvoidboard-level reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An underfill member is introduced as an intermediary substance between the lower package and upper package. This underfill member fills the space between the packages and provides mechanical support to the conductive connection members, preventing joint cracks caused by thermal stress while maintaining the POP stacking configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The underfill member is formed from a curable composition containing a base polymer, filler, and curing agent. This composite material structure provides both mechanical strength to prevent cracks and thermal management properties, resolving the reliability issue while maintaining the compact POP design

Inventive Principle:
Principle #40Composite materials

2Reliability

If conductive connection members are used to mount the upper package on the lower package, then electrical connection is achieved, but thermal stress causes joint cracks, reducing heat dissipation efficiency

Engineering Contradiction:
Improveelectrical connection stabilityVSAvoidheat dissipation efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The underfill member serves as a mediator that provides a thermally conductive path between the lower package and upper package. It fills the gaps and provides continuous thermal contact, improving heat dissipation efficiency while also protecting the conductive connection members from thermal stress-induced cracking

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The underfill member changes the thermal field distribution by providing a thermally conductive pathway. It alters the thermal parameters in the interface region between packages, enabling more efficient heat dissipation and reducing thermal stress concentration at the conductive connection members

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves board-level reliability and heat dissipation characteristics by preventing joint cracks in conductive connections and providing an effective heat dissipation path for the processor chip.

Implementation Method 1

an underfill member extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package

Methodology Applied
Scientific EffectAdhesive bonding: Adhesive

Implementation Method 2

serving as a heat dissipation path for heat dissipation of a processor chip of the lower package

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240429110A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2024.12.26 SAMSUNG ELECTRONICS CO LTD
  • US20240429110A1 patent drawing
  • US20240429110A1 patent drawing
  • US20240429110A1 patent drawing

AI summary

A semiconductor package includes a lower package having opposite first and second lower package sides that extend in a first direction; an upper package stacked on the lower package by conductive connection members, the upper package having opposite first and second upper package sides that extend in the first direction, wherein the second upper package side is spaced apart from the second lower package side by a predetermined distance to define an underfill region on an upper surface of the lower package; and an underfill member extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package.