Package-on-Package Semiconductor Via and Mark Formation
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Solution Overview
Problem
The laser marking process for semiconductor packages can damage the chip and reduce the visibility of the mark, leading to yield reduction in package stacking.
Innovation Solution
A method where a laser is used to form a via hole and a recognition mark on a portion of the lower mold layer between the via hole and the semiconductor chip, allowing for high visibility without damaging the chip, and the same laser is used for both processes in the same equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If laser intensity is increased to improve mark visibility, then mark visibility is improved, but semiconductor chip damage occurs
Solution Approach 1:
The patent segments the mold layer into different functional regions: a first region for via hole formation and a second region for marking. This allows selective laser application - high intensity for via holes and lower intensity for marking - thereby preventing chip damage while maintaining mark visibility.
Solution Approach 2:
The patent applies different laser intensities to different regions of the mold layer. The first region (via hole area) receives higher laser intensity for effective penetration, while the second region (marking area) receives lower laser intensity sufficient for marking but safe for the underlying chip. This local differentiation resolves the contradiction between visibility and damage prevention.
2Object-affected harmful factors
If laser intensity is decreased to prevent chip damage, then chip damage is prevented, but mark visibility is reduced
Solution Approach 1:
By dividing the mold layer into distinct functional zones (via hole region and marking region), the patent enables optimized laser parameters for each function. The marking region receives sufficient laser energy for visible marks without exceeding chip damage thresholds.
Solution Approach 2:
The patent implements spatially varying laser intensity distribution across the mold layer. The marking region is positioned where lower laser intensity achieves adequate visibility while inherently protecting the chip, eliminating the need to compromise visibility for safety.
3Manufacturing precision
If separate equipment is used for via hole formation and marking, then process precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs a single laser device that performs multiple functions: forming via holes in the first region and creating alignment marks in the second region. This multi-functional approach reduces equipment complexity and cost while maintaining precision through software-controlled parameter adjustment for different regions.
Solution Approach 2:
The patent combines via hole formation and marking operations into a single integrated process using one laser device. The laser beam is directed to different regions with different parameters in the same processing cycle, merging two previously separate operations into one unified process that reduces equipment requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents chip damage while maintaining mark visibility, improving the stacking yield and simplifying the fabrication process, reducing costs and equipment investment.
Implementation Method 1
irradiating a first laser onto the lower mold layer to form a via hole exposing the lower terminal
Implementation Method 2
irradiating a second laser onto the lower mold layer to form a laser mark
Data Source
AI summary
Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a lower package and a via provided between the lower and upper packages to electrically connect the lower and upper packages to each other. The lower package includes a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer encapsulating the lower semiconductor chip and including an alignment mark. The lower mold layer includes a marking region, which is provided between the via and the lower semiconductor chip, and on which the alignment mark is provided.