Power-On Reset Circuit With Transistor-Stack Delay and Low Static Power
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Solution Overview
Problem
Conventional power-on reset (POR) circuits in integrated circuits (ICs) face challenges in reducing static power consumption while maintaining accurate trip level accuracy and desired time delays, especially when dealing with low-power ICs and varying ramp-up rates of the supply voltage.
Innovation Solution
The proposed POR circuit utilizes a first transistor, a stack of transistors, and a logic circuit to generate a reset signal based on the enable voltage and trigger voltage, which are derived from the supply voltage. This configuration allows for a controlled ramp-up of the enable voltage, reducing the number of delay elements needed and preventing low impedance paths during steady state, thus minimizing steady-state current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If supplementary components are added to the POR circuit to achieve the desired delay, then the time delay is improved, but the device complexity and area increase
Solution Approach 1:
The patent combines the delay function with the existing POR circuit components by utilizing the charging characteristics of the start-up transistor and capacitor. The delay is achieved through the natural RC time constant of the circuit rather than adding separate delay components, thereby merging multiple functions into a unified structure.
Solution Approach 2:
The POR circuit uses its own internal components (start-up transistor, capacitor, and feedback path) to generate the required delay. The circuit self-regulates the delay period through the charging and discharging cycles of the capacitor controlled by the start-up transistor, eliminating the need for external delay elements.
2Duration of action of moving object
If supplementary components are added to the POR circuit to achieve the desired delay, then the time delay is improved, but the area increases
Solution Approach 1:
The delay functionality is merged with the essential POR circuit components. The capacitor that is already part of the POR circuit serves dual purposes: maintaining the reset signal and providing the delay timing function, thus avoiding additional area consumption for separate delay components.
Solution Approach 2:
The start-up transistor and capacitor are designed to perform multiple functions simultaneously: they initialize the circuit, maintain the reset signal during voltage transitions, and provide the required time delay. This multi-functionality reduces the overall component count and circuit area.
3Use of energy by stationary object
If the POR circuit is designed to reduce static power consumption, then the power consumption is improved, but the trip level accuracy deteriorates
Solution Approach 1:
The circuit employs feedback mechanisms where the output of the logic circuit feeds back to control the start-up transistor. This feedback ensures that the circuit maintains accurate trip level detection while in low-power standby mode, as the feedback path allows the circuit to monitor voltage levels without continuous power consumption.
Solution Approach 2:
The POR circuit operates in periodic cycles: during normal operation, it remains in a low-power standby state; when voltage transitions occur, it activates to generate the reset signal. This periodic activation reduces average power consumption while maintaining trip level accuracy during critical detection moments.
4Use of energy by stationary object
If the POR circuit is designed to reduce static power consumption, then the power consumption is improved, but the ability to provide desired time delay deteriorates
Solution Approach 1:
The circuit generates its own delay timing using the inherent charging characteristics of the capacitor and the controlled operation of the start-up transistor. The delay is self-regulated through the circuit's own components without requiring continuous external power or additional active components that would increase static power consumption.
Solution Approach 2:
The delay mechanism operates periodically based on voltage transitions. The capacitor charges and discharges in response to supply voltage changes, automatically generating the required delay period only when needed, thus maintaining low static power consumption while providing adequate delay during active transitions.
Data Source
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AI summary
A power-on reset (POR) circuit includes a first transistor and a stack of transistors. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced version of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The stack of transistors generates a control voltage. The control voltage is a reduced version of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the stack of transistors in a first time period. Further, a reset signal generated by the POR circuit is asserted when the enable voltage exceeds the first threshold voltage at the end of the first time period.