POR Delay Circuit Using Voltage Drop for Low-Area Reset Timing
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Solution Overview
Problem
Existing power on reset (POR) circuits require significant die or board space and consume continuous DC current, making them unsuitable for low power applications and increasing area requirements.
Innovation Solution
A modified POR circuit design incorporating a voltage drop device in series with a switching device and a capacitance device to set the delay time, reducing on-resistance and area requirements, while consuming nearly zero current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional POR circuits are used, then reliable power-on reset function is achieved, but die area and board space are significantly increased
Solution Approach 1:
The patent changes the operating parameters of the switching device by introducing a voltage drop device that reduces the voltage across the switching device, thereby increasing its on-resistance. This parameter change allows the use of smaller capacitance values to achieve the same delay time, reducing the overall circuit area while maintaining reliable POR function.
Solution Approach 2:
The patent applies local quality by creating a non-uniform voltage distribution across the switching device through the voltage drop device. This localized voltage reduction at a specific point in the circuit allows the switching device to operate with higher effective resistance, enabling area reduction without compromising the overall POR reliability.
2Reliability
If traditional POR circuits are used, then power-on reset functionality is provided, but continuous DC current is consumed
Solution Approach 1:
The patent implements periodic action by using the voltage drop device to create a time-varying voltage condition across the switching device during the power-on sequence. The switching device operates in a dynamic manner rather than maintaining continuous conduction, thereby eliminating steady-state DC current consumption while preserving the reset functionality during the critical power-on period.
Solution Approach 2:
The patent dynamically changes the voltage parameter across the switching device using the voltage drop device, transforming the switching device's operating state from a continuous conduction mode to a transient operation mode. This parameter change eliminates continuous DC current paths while maintaining the necessary reset function during power-on.
3Loss of energy
If switching device with low on-resistance is used, then power loss is reduced, but delay time control becomes less effective
Solution Approach 1:
The patent introduces a voltage drop device as an intermediary element between the power supply and the switching device. This intermediary creates a controlled voltage reduction that effectively increases the switching device's on-resistance, enabling precise delay time control through the RC time constant formed by the switching device and capacitance device, while the actual power loss remains low due to the reduced voltage across the switching device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified POR circuit achieves reduced area usage and zero power consumption, operating over wide supply voltage and temperature ranges with scalable delay times, suitable for low power applications.
Implementation Method 1
a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time
Implementation Method 2
the voltage drop device is configured to reduce a voltage received by the switching device. the reduced voltage received by the switching device causes the on-resistance of the switching device to increase
Data Source
AI summary
One example discloses a power on reset (POR) circuit, including: an input configured to receive a power supply voltage; a delay circuit configured to output a first signal to a set of logic circuits prior to a delay time; wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time; wherein the delay circuit includes a voltage drop device coupled to receive the power supply voltage, a switching device having an on-resistance and coupled to the voltage drop device, and a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time.