Dual-Detector Power-On Reset Circuit for Zero Standby Current
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Solution Overview
Problem
Conventional power-on reset (POR) circuits in integrated circuits (ICs) consume non-zero steady-state current due to low impedance paths between supply voltage and ground, leading to increased power consumption and inefficiency, and fail to accurately detect both ramp-up and ramp-down trigger scenarios.
Innovation Solution
The POR circuit employs two separate trip detector circuits to generate trip node and reference voltages based on the supply voltage, using diode-connected transistors and control transistors to adjust these voltages, ensuring accurate detection of ramp-up and ramp-down trigger points while maintaining zero steady-state current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional POR circuits use low impedance paths between supply voltage and ground to generate reset signals, then reset signal generation is achieved, but steady-state current consumption increases
Solution Approach 1:
The patent implements dynamic control of the trip detector circuit's impedance state. During power-up, the circuit transitions from a high-impedance state to a low-impedance state to generate the reset signal, then returns to high-impedance to eliminate steady-state current. This dynamic state change allows the circuit to achieve reset signal generation temporarily without sustaining current flow.
Solution Approach 2:
The POR circuit operates in periodic cycles: during power-up, it activates the low-impedance path to generate the reset signal, then deactivates it to return to high-impedance state. This periodic activation ensures reset signal generation occurs only when needed (during voltage ramp-up), eliminating continuous steady-state current consumption while maintaining reliability.
2Device complexity
If conventional POR circuits use single trip detector configuration, then circuit simplicity is maintained, but detection accuracy for both ramp-up and ramp-down scenarios is insufficient
Solution Approach 1:
The patent segments the trip detection function into two distinct detectors: a first trip detector configured to detect the first trigger scenario (e.g., voltage rising above threshold during power-up) and a second trip detector configured to detect the second trigger scenario (e.g., voltage falling below threshold during power-down). This segmentation allows each detector to be optimized for its specific detection scenario, achieving high accuracy for both ramp-up and ramp-down events while maintaining clear functional separation.
Data Source
AI summary
A power-on reset (POR) circuit includes first and second trip detector circuits. The first trip detector circuit generates a reset signal indicative of a state of a supply voltage based on a trip node voltage that ramps up when the supply voltage ramps up. The reset signal is asserted when the trip node voltage exceeds a threshold value. The second trip detector circuit generates a control signal based on the supply voltage and a reference voltage. The reference voltage is less than the supply voltage until the supply voltage ramps down. During the ramp-down of the supply voltage, the supply voltage falls below the reference voltage, and the control signal is asserted when the supply voltage is less than the reference voltage by a different threshold value. The asserted control signal results in the trip node voltage being altered such that the reset signal is de-asserted.