Power-On Reset Latch Circuit With Capacitive Skew and Diode Holdoff
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Solution Overview
Problem
Existing power on reset (POR) circuits in integrated circuits consume excessive power, particularly in battery-operated devices, as they require constant active power to generate reliable reset signals during power up, which is inefficient and problematic for low power operation.
Innovation Solution
A power on reset latch circuit design that includes a capacitively skewed latch and diodes to maintain a known latch state during power up, with a level shifter circuit providing control signals once the second voltage domain is powered, ensuring reliable POR signals while minimizing power consumption by preventing state changes until the voltage supply reaches a minimum threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an active power circuit is used to generate reliable reset signals during power up, then the reliability of reset signals is improved, but the power consumption increases
Solution Approach 1:
The circuit uses capacitive skewing to pre-establish a known latch state during power-up before the voltage reaches threshold levels. The capacitors are charged during power-up and automatically discharge to force the latch into a predetermined state, eliminating the need for continuous active power circuit operation.
Solution Approach 2:
The latch circuit uses its own internal capacitive elements and power supply voltage to automatically set its initial state during power-up. The circuit serves itself by using the power supply ramp to charge capacitors that naturally force the latch into the desired state without external intervention or continuous power consumption.
2Adaptability or versatility
If the latch circuit allows state changes during power up, then the circuit responds dynamically to voltage changes, but the latch state becomes unpredictable
Solution Approach 1:
The circuit employs asymmetric capacitive coupling where one side of the latch has a capacitor connected to the Q output and the other side has a capacitor connected to the Q-bar output. This asymmetric configuration creates unequal charging paths that force the latch into a specific known state during power-up, preventing unpredictable behavior while maintaining dynamic responsiveness.
Solution Approach 2:
The circuit exploits changes in capacitance charging states during the power-up voltage ramp. As the power supply voltage increases, the capacitors charge at different rates and to different levels, creating a transient condition that naturally drives the latch into a predetermined state. This parameter change approach ensures predictable initialization without restricting dynamic operation once powered.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively generates a reliable POR signal upon power up while reducing power consumption by maintaining the latch state until the voltage supply reaches a minimum threshold, ensuring efficient low power operation in battery-operated devices.
Implementation Method 1
a diode inhibiting current flow in the first current path between the first latch node and the power supply terminal when the power supply voltage differential is below a threshold voltage during power up
Implementation Method 2
a capacitor coupled to the first latch node and inhibiting current flow to the latch node when the power supply voltage differential is below a threshold voltage during power up
Data Source
AI summary
A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.