Power-On-Reset Circuit Using Oscillator Shutdown for Zero Static Power
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Solution Overview
Problem
Conventional power-on-reset (POR) circuits consume non-zero current even in low power modes, posing challenges in applications requiring low power consumption, and existing solutions do not adequately address the POR circuit's behavior in power-down states.
Innovation Solution
A POR circuit design incorporating a state machine, oscillator, and output circuitry that operates at zero or substantially zero current by generating a reset signal based on Boolean states, allowing the circuit to remain active with minimal power consumption, even in power-down states, using a cascade of flip-flops and inverters to ensure consistent initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional POR circuits are used to ensure reliable system initialization, then system reliability is improved, but power consumption increases in low-power modes
Solution Approach 1:
The POR circuit dynamically adjusts its operational state based on power-down input signals. The state machine transitions between active and low-power states, enabling the circuit to maintain reliability when needed while minimizing power consumption during low-power modes. This is achieved through dynamic control of the oscillator and output circuitry based on the power-down detection logic.
Solution Approach 2:
The circuit changes its operational parameters by responding to power-down input signals. When power-down inputs are detected, the circuit modifies its behavior to consume minimal power while still maintaining the ability to generate reset signals when voltage thresholds are crossed. This parameter change allows the circuit to adapt between high-reliability and low-power states.
2Reliability
If POR circuit remains always active to generate reset signals, then system initialization is ensured, but power consumption increases
Solution Approach 1:
The oscillator generates clock signals periodically to drive the state machine, but only when power-down inputs are not detected. This periodic operation allows the circuit to maintain reset generation capability when needed while consuming minimal power during normal operation. The oscillator is disabled during low-power modes, eliminating continuous power consumption.
Solution Approach 2:
The power-consuming components (oscillator and output circuitry) are extracted from continuous operation and activated only when power-down inputs are detected. This separation allows the circuit to maintain the essential reset generation function while eliminating unnecessary power consumption during normal operation.
3Use of energy by moving object
If power-down mode is implemented to reduce power consumption, then battery life is extended, but POR circuit may fail to initialize properly
Solution Approach 1:
The circuit implements feedback through power-down detection logic that monitors power-down inputs and adjusts oscillator operation accordingly. This feedback mechanism ensures that the POR circuit remains functional during power-down modes by preventing the oscillator from operating when it would cause improper initialization, while still allowing reset generation when voltage thresholds are crossed.
Solution Approach 2:
The circuit performs preliminary detection of power-down inputs before attempting to generate reset signals. This preliminary action prevents improper initialization by checking the power-down state before activating the oscillator and output circuitry, ensuring that reset signals are only generated when appropriate.
Data Source
AI summary
A power-on-reset (POR) circuit having a zero or substantially zero current state while the supply voltage is in a predetermined, valid range is disclosed. The POR circuit includes a state machine, an oscillator, and output circuitry that are electrically coupled to one another and to a supply voltage. Output from the output circuitry is also provided to the integrated circuit to which the POR circuit is coupled. The state machine includes a plurality of sequential circuits such as latches, flip-flops, and the like that are electrically coupled in a cascade, to provide a ripple counter. The output circuitry is structured and arranged to reset or initialize all of the logic elements on the chip by generating a POR output logic HI (1) signal by Boolean operation of the logic circuitry signal of the state machine for all Boolean states except one. The oscillator is disabled when the POR output logic signal is LO (0), which causes the POR circuit to enter a zero or substantially zero current state.