On-Chip POR Pulse Generation With Low-Noise Reset Timing
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Solution Overview
Problem
Reducing the area and complexity of on-chip circuits that generate power on reset (POR) pulses while minimizing inter-module and inter-chip noise is challenging in integrated circuits like System on Chips (SoCs).
Innovation Solution
The integration of a power supply sense circuit, pulse generation circuit, and reset generation circuit, utilizing voltage dividers, MOS transistors, inverter circuits, delay blocks with Miller amplifiers, and Schmitt trigger buffers to generate a POR pulse of specific duration for resetting circuit elements, such as flip-flops and memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a power on reset (POR) pulse is generated on-chip, then noise immunity is improved, but circuit area and complexity increase
Solution Approach 1:
The POR generation circuit is divided into multiple functional blocks: a power supply sensing block that detects voltage transitions, a pulse generation block that creates the POR pulse, and a delay block that controls pulse width. This segmentation allows each block to be optimized independently, reducing overall complexity while maintaining noise immunity benefits of on-chip generation.
Solution Approach 2:
The POR generation circuit is designed to work with multiple power supply voltages and different circuit configurations within the SoC. The sensing block can detect transitions on different voltage rails, and the pulse generation logic is configured to produce appropriate POR signals for various memory devices and logic blocks, reducing the need for separate POR circuits for each component.
2Ease of manufacture
If circuit area is reduced, then manufacturing cost decreases, but POR pulse generation reliability deteriorates
Solution Approach 1:
The circuit employs dynamic element sizing where transistor widths and capacitor values are optimized based on their specific functional requirements rather than using uniform sizing throughout. Critical components involved in pulse detection and generation use larger dimensions for higher reliability, while less critical routing and control elements use minimal area implementations, achieving an optimal balance between reliability and area.
Solution Approach 2:
The patent introduces intermediate sensing nodes and buffer stages that mediate between the power supply voltage transitions and the final POR pulse output. These intermediary elements amplify and condition the signal, ensuring reliable pulse generation even with minimal area implementation, while also providing noise filtering that enhances signal integrity.
Data Source
AI summary
Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.