Power-On Reset Circuit Using Threshold Tracking for Stable Release
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Solution Overview
Problem
Power-on reset (POR) circuits in integrated circuits face challenges in transitioning between reset states due to variations in process and temperature, requiring a fixed supply voltage and timing margins that are not adaptive to these changes.
Innovation Solution
A POR circuit that uses VDD/VT threshold circuitry to provide scaled threshold voltages based on transistor Vtp and Vtn, coupled with POR transition detect and control circuitry to manage state transitions independently of VDD ramp slew rate, ensuring reliable reset transitions across temperature and manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed supply voltage and timing margins are used for POR transitions, then the circuit design is simple, but the reset transitions become unreliable under process and temperature variations
Solution Approach 1:
The POR circuit dynamically adjusts the transition threshold voltage based on process and temperature variations. The circuit uses a voltage reference that scales with the supply voltage VDD and compensates for transistor threshold voltage variations, allowing the reset transition point to adapt to changing operating conditions rather than using a fixed threshold.
Solution Approach 2:
The circuit changes the reference voltage parameter dynamically to match process and temperature variations. By using a voltage reference that tracks VDD and transistor threshold voltages, the circuit adjusts its operating parameters in real-time to maintain reliable reset transitions across different process corners and temperature ranges.
2Reliability
If timing margins are increased to ensure reliable reset transitions, then reset reliability improves, but the IC startup time increases
Solution Approach 1:
The circuit dynamically determines the optimal transition point based on actual voltage conditions rather than using conservative fixed timing margins. By detecting when VDD reaches the adaptive threshold voltage, the circuit can transition at the precise moment when registers are stable, eliminating unnecessary delay while ensuring reliability.
Solution Approach 2:
The POR circuit uses its own internal voltage detection capability to determine when transition is safe, eliminating the need for external timing control or conservative margins. The circuit serves itself by monitoring VDD and automatically transitioning when conditions are met, reducing startup time while maintaining reliability.
3Stability of the object's composition
If the POR circuit transitions out-of-reset when VDD ramps sufficiently, then register stability is ensured, but the transition point varies with VDD ramp slew rate
Solution Approach 1:
The circuit changes its reference parameter from a fixed voltage to a scaled voltage that tracks VDD and transistor threshold variations. The voltage reference circuit adjusts its output proportionally to VDD, ensuring the transition threshold adapts to different VDD ramp rates and process conditions while maintaining the stability requirement.
Data Source
AI summary
A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.