Pore Sealing Layer for Cu/Low-k Interconnects
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Solution Overview
Problem
Porous dielectrics in semiconductor manufacturing are susceptible to damage during plasma etching and wet cleaning processes, leading to increased leakage currents, lower breakdown voltages, and changes in the dielectric constant, necessitating improved low-k dielectric manufacturing methods.
Innovation Solution
A semiconductor device fabrication process involving the formation of a porous dielectric layer with a pore sealing layer, where the pore sealing layer has a substantially non-uniform thickness and is composed of materials like carbon-doped silicon dielectric, formed using SACVD or PECVD, to protect the porous dielectric from plasma damage and moisture uptake.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etching processes are used on porous dielectrics, then interconnect patterning can be achieved, but the porous dielectric layer suffers damage leading to increased leakage currents and lower breakdown voltages
Solution Approach 1:
A pore sealing layer is deposited on the porous dielectric layer before plasma etching to prevent plasma damage. This preliminary protective action ensures the porous dielectric is shielded from harmful plasma exposure during subsequent etching processes, maintaining both patterning precision and dielectric reliability
Solution Approach 2:
The pore sealing layer acts as an intermediary between the plasma etching process and the porous dielectric layer. This intermediate layer allows plasma to pass through for effective etching while simultaneously protecting the porous dielectric from damage, resolving the contradiction between manufacturing precision and reliability
2Manufacturing precision
If conventional wet cleaning methods are used on porous dielectrics, then surface contamination can be removed, but cleaning fluids enter pores causing corrosion and increased dielectric constant
Solution Approach 1:
The pore sealing layer is deposited before wet cleaning to prevent cleaning fluids from entering the porous dielectric pores. This preliminary protective measure allows effective surface cleaning while preventing corrosion and moisture absorption that would otherwise occur
Solution Approach 2:
The pore sealing layer serves as an intermediary barrier during wet cleaning operations, enabling contamination removal while blocking cleaning fluids from penetrating into the porous structure, thus preventing corrosion and dielectric constant changes
3Reliability
If porous dielectric materials are used to achieve low dielectric constants, then RC delay is reduced, but the materials become more susceptible to plasma and chemical damage
Solution Approach 1:
The pore sealing layer is deposited in advance to protect the porous dielectric from plasma and chemical damage. This preliminary protection enables the use of low-k porous materials for improved circuit performance while mitigating their inherent susceptibility to processing damage
Solution Approach 2:
The pore sealing layer acts as an intermediary protective barrier that allows the porous dielectric to maintain its low dielectric constant properties for improved RC delay while simultaneously protecting it from plasma and chemical susceptibility during manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively reduces line-to-line leakage and increases time-dependent dielectric breakdown (TDDB) lifetime by preventing plasma damage and moisture absorption, while maintaining low intrinsic stress levels and providing good step coverage.
Implementation Method 1
forming a pore sealing layer over sidewalls of the opening
Implementation Method 2
formed using SACVD or PECVD
Implementation Method 3
A hydrophilic surface tends to absorb moisture
Data Source
AI summary
A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.