Porous Buffer Layer for Large Grain Polysilicon
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Solution Overview
Problem
Conventional methods for forming polysilicon layers on substrates for TFT-LCDs result in smaller grain sizes, limiting electron mobility due to rapid thermal energy dissipation and short crystallization duration, which affects the performance of thin film transistors.
Innovation Solution
Doping inert gases into the substrate or buffer layers to create pores, reducing thermal conductivity, and using a multi-layer buffer structure to extend crystallization time, allowing for the formation of larger grain size polysilicon layers through excimer laser annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional PECVD and laser annealing methods are used to form polysilicon layers, then the substrate temperature can be controlled below 250°C, but the grain size of polysilicon remains small due to rapid thermal energy dissipation
Solution Approach 1:
The patent introduces a porous buffer layer with controlled pore density (10^18 to 10^20 pores/cm³) and pore diameter (0.1 to 10 μm) between the substrate and amorphous silicon layer. This porous structure reduces thermal conductivity, slowing heat dissipation during laser annealing and extending the time for crystal grain growth, thereby achieving larger polysilicon grain size while maintaining substrate temperature control
Solution Approach 2:
The porous buffer layer acts as a thermal intermediary with reduced thermal conductivity compared to conventional dense buffer layers. It mediates heat transfer from the amorphous silicon layer during laser annealing, reducing rapid thermal energy dissipation into the substrate and enabling extended crystallization time for larger grain formation
2Reliability
If the buffer layer has high thermal conductivity to efficiently remove heat from the substrate, then substrate temperature control is improved, but the crystallization duration is limited resulting in smaller grain size
Solution Approach 1:
The buffer layer is engineered with specific porosity (10^18 to 10^20 pores/cm³) to reduce thermal conductivity while maintaining structural integrity. This porous configuration creates a thermal barrier that extends heat retention time in the amorphous silicon layer during laser annealing, thereby prolonging crystallization duration without compromising substrate temperature control
Solution Approach 2:
The patent modifies the thermal conductivity parameter of the buffer layer by controlling pore density, pore diameter, and porosity ratio (10% to 50%). These parameter changes optimize the balance between heat removal from substrate and heat retention for crystallization, extending crystallization duration to achieve larger grain size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves larger grain size polysilicon layers with improved uniformity and increased electron mobility in TFT arrays, enhancing the performance of thin film transistors.
Implementation Method 1
the inert gas is first doped into the substrate to form a number of pores in the substrate
Implementation Method 2
a laser beam is emitted onto the amorphous silicon layer. Laser beam serves as a thermal resource to heat and convert amorphous silicon into polysilicon layer
Implementation Method 3
The laser beam with a wavelength of 308 nm combined with ELA technique is used to crystallize the amorphous silicon layer
Implementation Method 4
the amorphous silicon layer is heated and then being converted into a polysilicon layer
Implementation Method 5
the amorphous silicon layer is heated to convert the amorphous silicon layer into a polysilicon layer
Data Source
AI summary
In a method of forming a polysilicon layer on a substrate, a first embodiment comprises: doping inert gas into the substrate to form a plurality of pores in the substrate; depositing a buffer later on the substrate; depositing an amorphous silicon layer on the buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer. A second embodiment comprises: depositing a first buffer layer on a substrate; doping inert gas into the first buffer layer to form a plurality of pores in the first buffer layer; depositing a second buffer layer on the first buffer layer; depositing an amorphous silicon layer on the second buffer layer; and heating the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer.