Porous CMP Polishing Composition for High Rate, Low Defects

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Solution Overview

Problem

Existing semiconductor polishing compositions face challenges in achieving a high polishing rate while minimizing defects such as dishing and erosion, particularly in CMP processes where the surface structure is complex and requires precise planarization.

Innovation Solution

A polishing composition comprising polishing particles with controlled Rps values, specific surface areas, and micropore characteristics, along with additives like nonionic polymers and chelating agents, to enhance polishing efficiency and reduce defect formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional polishing compositions are used to achieve high polishing rate, then polishing speed is improved, but dishing and erosion defects increase

Engineering Contradiction:

Improvepolishing rateVSAvoiddishing and erosion defects

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The polishing particles are designed with a porous structure having specific pore volume (0.03-0.08 mL/g) and pore size distribution (0.003-0.05 μm). This porous structure increases the specific surface area for chemical interaction while distributing mechanical stress more evenly, thereby maintaining high polishing rate through enhanced chemical reactivity while reducing dishing and erosion caused by concentrated mechanical forces

Inventive Principle:

Principle #31Porous materials

Solution Approach 2:

The polishing composition uses composite polishing particles made of silica-based material with controlled porous structure and surface properties. The composite nature of the particles, combining appropriate porosity with surface chemistry, enables simultaneous achievement of high polishing rate through chemical mechanical action and reduced defects through stress distribution and controlled particle-substrate interaction

Inventive Principle:

Principle #40Composite materials

2Productivity

If polishing particles with high surface area are used to increase polishing rate, then productivity is improved, but particle interaction control becomes more difficult leading to increased defects

Engineering Contradiction:

Improvepolishing rateVSAvoiddefect reduction

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The polishing particles are engineered with specific parameter ranges: pore volume of 0.03-0.08 mL/g, pore size of 0.003-0.05 μm, and Rps ratio of 0.1-0.5. These controlled parameters optimize the balance between surface area (for polishing rate) and particle interaction characteristics (for defect reduction), ensuring reliable polishing performance

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If complex surface structures with large step differences are polished, then manufacturing capability is improved, but achieving uniform planarization becomes more difficult

Engineering Contradiction:

Improvecapability to handle complex surfacesVSAvoidplanarization uniformity

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The porous polishing particles provide locally varied interaction characteristics through their pore structures, enabling different regions of the particle surface to interact differently with the substrate. This local quality variation allows the particles to adapt to complex surface topographies with large step differences while maintaining uniform planarization through distributed chemical mechanical action across varying surface conditions

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The composition achieves excellent polishing rates with reduced defects, providing stable and effective planarization for semiconductor substrates by controlling particle interaction and surface roughness.

Implementation Method 1

slurry is supplied to a polishing pad while the substrate is pressed and rotated, and the surface is polished

Methodology Applied

Scientific EffectAbrasion: Abrasion

Implementation Method 2

Ap is the micropore specific surface area of the polishing particles, and As is the external specific surface area of the polishing particles

Methodology Applied

Scientific EffectAdsorption: Adsorption

Data Source

PatentEP4678707A1Polishing composition for semiconductor process, and method for polishing substrate by using same

Publication Date: 2026.01.14 YOUNG CHANG CHEMICAL CO LTD

Figure 1

AI summary

A polishing composition for semiconductor process according to one embodiment of the present specification comprises polishing particles. An Rps value, which is a ratio of a micropore specific surface area to an external specific surface area of the polishing particles according to the following Formula 1, is 0.5 to 2. Rps=ApAs In Formula 1, Ap is a micropore specific surface area of the polishing particles, and As is an external specific surface area of the polishing particles. When such a polishing composition for semiconductor process is applied to a CMP polishing process, it may exhibit excellent polishing rate and may provide a polished surface with reduced defects.