Porous Connecting Structure for Semiconductor Signal Interference

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Solution Overview

Problem

The challenge in scaling down semiconductor devices is to achieve improved quality, yield, performance, and reliability while reducing complexity, particularly in connecting structures that affect electrical signal interference and device integration.

Innovation Solution

A semiconductor device design featuring a connecting structure with a porous layer between conductive layers, formed by an energy-removable material that is treated to create porosity between 25% and 100%, allowing for reduced parasitic capacitance and efficient signal transmission, and enabling the connection of multiple devices with enhanced functionality in a compact form.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional connecting structures are used in scaled-down semiconductor devices, then device integration is achieved, but electrical signal interference and parasitic capacitance increase

Engineering Contradiction:

Improveelectrical signal interferenceVSAvoidconnecting structure complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent introduces a porous layer within the connecting structure that has reduced dielectric constant due to its porous nature. This porous material reduces parasitic capacitance between conductive layers while maintaining structural integrity, thereby decreasing electrical signal interference without significantly increasing device complexity

Inventive Principle:

Principle #31Porous materials

Solution Approach 2:

The connecting structure employs composite materials combining conductive layers with porous dielectric materials. This composite approach allows optimization of electrical properties (reduced interference) while managing structural complexity through integrated material design

Inventive Principle:

Principle #40Composite materials

2Productivity

If device dimensions are scaled down to improve computing ability, then computing performance is enhanced, but manufacturing precision and reliability become more difficult to maintain

Engineering Contradiction:

Improvecomputing abilityVSAvoidfabrication precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the physical parameters of the connecting structure by introducing porosity, which alters the dielectric constant and electrical characteristics. This parameter change allows maintaining electrical performance at smaller dimensions while simplifying fabrication through controlled porous layer formation

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The porous layer provides a structure that is easier to fabricate at small scales while maintaining electrical isolation. The porous structure reduces manufacturing precision requirements compared to solid dielectric layers at the same scale, as it tolerates variations better while achieving the desired electrical isolation

Inventive Principle:

Principle #31Porous materials

3Volume of moving object

If connecting structures are designed for compact form factor, then device size is reduced, but electrical signal interference increases

Engineering Contradiction:

Improvedevice volumeVSAvoidelectrical signal interference

Core Design Contradiction:

Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The porous layer embedded in the compact connecting structure provides electrical isolation between closely spaced conductive layers. The reduced dielectric constant of the porous material decreases parasitic capacitance, thereby reducing electrical signal interference even in the compact form factor

Inventive Principle:

Principle #31Porous materials

Solution Approach 2:

The patent introduces porosity as an additional dimensional characteristic within the connecting structure. This vertical porosity distribution allows electrical isolation without increasing horizontal device footprint, enabling compact form factor while maintaining electrical performance

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces electrical signal interference, allows for more sophisticated functions in a smaller form factor, and lowers production costs by enabling the connection of multiple semiconductor devices while maintaining performance and reliability.

Implementation Method 1

A porosity of the first porous layer is between about 25% and about 100%

Methodology Applied

Scientific EffectPorosity: Porosity

Data Source

PatentUS11527512B2Method for fabricating semiconductor device with connecting structure

Publication Date: 2022.12.13 NAN YA TECH

AI summary

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, two first conductive layers in the first connecting insulating layer, and a first porous layer between the two first conductive layers; wherein a porosity of the first porous layer is between about 25% and about 100%.