Porous Copper Metallization for Semiconductor Chip Stress Reduction
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Solution Overview
Problem
Conventional methods for reducing sheet resistance in semiconductor chips by thinning the material increase vulnerability to cracking and require costly and time-intensive backside metallization processes, which introduce thermomechanical stress and electrical resistance issues.
Innovation Solution
A method involving forming recesses in the substrate with porous copper metallization and solder material to create a stable chip-taiko structure, reducing thermomechanical stress and manufacturing effort while maintaining low electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the semiconductor material is reduced to decrease sheet resistance, then the electrical resistance is improved, but the vulnerability to cracking and bending increases
Solution Approach 1:
The patent applies local quality by creating a chip-taiko-rim structure where only specific regions (perimeter and active area) have different thicknesses. The perimeter region maintains greater thickness for mechanical strength while the active area is thinned for electrical performance, allowing simultaneous optimization of both fracture strength and sheet resistance in different locations of the same chip.
2Reliability
If copper backside metallization is used to fill the cavity, then the electrical resistance is reduced, but the manufacturing time and cost increase
Solution Approach 1:
The patent employs porous copper material to fill the cavity in the active area. This porous structure provides adequate electrical conductivity while significantly reducing the amount of copper material needed compared to solid backside metallization. The porous structure also reduces thermomechanical stress due to its lower density and compliance, thereby decreasing manufacturing complexity and time while maintaining acceptable electrical resistance.
3Ease of manufacture
If solder material is used to fill the cavity, then the manufacturing effort is reduced, but the electrical resistance and thermal resistance increase
Solution Approach 1:
The patent creates a composite structure by combining porous copper with solder material in the cavity filling. The porous copper provides a conductive framework with lower electrical resistance than solid solder, while the solder material fills the pores and provides mechanical bonding. This composite approach achieves a balance between ease of manufacture (solder's advantage) and electrical/thermal performance (copper's advantage), reducing both electrical resistance and thermal resistance compared to using solder alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces thermomechanical stress and manufacturing costs while maintaining low electrical resistance and high thermal conductivity, enhancing the stability and performance of semiconductor chips.
Implementation Method 1
forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls
Data Source
AI summary
According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.