Porous Dielectric Interconnect Etching With SiO2 Mask Protection
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Solution Overview
Problem
Existing semiconductor fabrication methods face challenges in achieving high integration density and reducing parasitic capacitance between interconnection patterns while maintaining porosity and dielectric constant of porous dielectric layers, leading to potential etch damage and void formation.
Innovation Solution
A method involving sequential stacking and etching of mask layers on a substrate, using carbon-free silicon oxide for the first mask layer and SiOCH for the porous dielectric layer, with controlled etching steps to form grooves and interconnection patterns, ensuring minimal porosity loss and reduced reciprocal aspect ratio of grooves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching methods are used to form interconnection patterns, then manufacturing process is simpler, but etch damage occurs and voids form in the porous dielectric layer
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etching conditions. The first etching step uses a first etching condition to form initial grooves, the second etching step uses a second etching condition to continue etching to form final interconnection patterns. This segmentation allows optimization of each step to prevent etch damage and void formation while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes etching parameters between steps, specifically using different etching conditions (such as different gas compositions, pressures, or power levels) in the first and second etching steps. This parameter change enables precise control of the etching process to prevent etch damage and void formation in the porous dielectric layer
2Productivity
If the number of interconnection patterns per unit area is increased to enhance integration density, then integration density improves, but parasitic capacitance between interconnection patterns increases
Solution Approach 1:
The patent uses a porous dielectric layer with controlled porosity (30-70%) as the insulation material between interconnection patterns. The porous structure reduces the dielectric constant of the insulating layer, thereby reducing parasitic capacitance between closely-spaced interconnection patterns while maintaining high integration density
Solution Approach 2:
The dielectric layer is formed as a composite structure containing porous silicon oxide and organic material (such as PMMA or resist). This composite material provides both the necessary mechanical support and the low dielectric constant properties needed to reduce parasitic capacitance
3Object-generated harmful factors
If porosity of the dielectric layer is maintained high to reduce dielectric constant, then parasitic capacitance reduces, but etch damage and void formation occur more easily
Solution Approach 1:
A mask layer is formed on the porous dielectric layer before etching to provide protection during the etching process. This preliminary protective action prevents etch damage and void formation in the porous dielectric layer while allowing the high porosity structure to be maintained for low parasitic capacitance
Solution Approach 2:
The mask layer acts as an intermediary between the etching process and the porous dielectric layer. It mediates the etching process by providing a protective barrier that prevents direct etchant contact with the porous dielectric layer, thereby preventing etch damage and void formation while allowing the porous structure to be preserved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density by increasing the number and reducing the width of interconnection patterns, maintains low dielectric constant, and prevents void formation, thereby improving semiconductor device reliability and yield.
Implementation Method 1
a dielectric constant of the first porous dielectric layer is smaller than a dielectric constant of the second porous dielectric layer
Implementation Method 2
etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves
Data Source
AI summary
A method of fabricating a semiconductor device and a device fabricated thereby, the method including sequentially stacking an interlayer insulating layer, a porous dielectric layer, a first mask layer, and a second mask layer on a substrate; etching the second mask layer to form preliminary mask patterns; etching the preliminary mask patterns to form second mask patterns; etching the first mask layer using the second mask patterns as an etch mask to form first mask patterns; etching the porous dielectric layer using the first mask patterns as an etch mask to form grooves; and forming interconnection patterns in the grooves, respectively, wherein the porous dielectric layer includes SiOCH, and the first mask layer includes carbon-free silicon oxide (SiO2).