Porous Gate Spacer Structure for Lower RC Delay in Semiconductors
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving improved quality, yield, and performance while reducing complexity and RC delay, particularly due to scaling issues that affect the coupling capacitance and operating current consumption.
Innovation Solution
The implementation of a semiconductor device design featuring a gate structure with porous spacers, a specific porosity range, and a flat top surface, which reduces coupling capacitance and operating current consumption, and enhances carrier mobility through stress regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device structures are used, then manufacturing process is simpler, but RC delay increases and performance deteriorates
Solution Approach 1:
The patent introduces porous spacers with controlled porosity (30-70%) formed through energy treatment of energy-removable material. These porous structures reduce coupling capacitance between gate and source/drain regions, thereby reducing RC delay and improving device performance while maintaining a manageable fabrication process
Solution Approach 2:
The patent changes the physical and chemical parameters of the spacer material through energy treatment (thermal, photonic, or e-beam energy). This transforms the energy-removable material into a porous structure with specific porosity parameters (30-70%), optimizing the balance between capacitance reduction and process complexity
2Productivity
If device dimensions are scaled down, then computing ability improves, but coupling capacitance and RC delay increase
Solution Approach 1:
The porous spacers with 30-70% porosity create low-dielectric-constant regions that reduce coupling capacitance between the gate structure and source/drain regions. This effectively reduces RC delay in scaled-down devices, enabling continued improvement in computing ability without being bottlenecked by capacitance effects
Solution Approach 2:
The porous spacers act as intermediary structures between the gate and source/drain regions. These spacers with controlled porosity serve as a mediating layer that reduces the direct capacitive coupling, allowing the device to achieve better performance at scaled dimensions
3Ease of manufacture
If conventional spacer structures are used, then manufacturing is easier, but operating current consumption increases
Solution Approach 1:
The patent applies energy treatment to change the physical parameters of the energy-removable material, transforming it into a porous structure with 30-70% porosity. This parameter change reduces the dielectric constant of the spacer, lowering coupling capacitance and thereby reducing operating current consumption while adding only one process step to fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces RC delay, improves yield and quality, and enhances performance by minimizing parasitic capacitance and optimizing current consumption, while facilitating subsequent processing with a flat top surface.
Implementation Method 1
The energy treatment may include, but is not limited to, thermal energy, photonic energy, or electron beam energy. In one embodiment, the energy treatment comprises a thermal treatment that thermally decomposes the organic material
Implementation Method 2
the porous spacers may reduce a coupling capacitance between the gate structure and the source/drain regions
Data Source
AI summary
The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.