Porous Interlayer Insulating Layer Air Gap Fabrication
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Solution Overview
Problem
As semiconductor devices become more integrated and their capacity increases, the reduced pitches of metal interconnections lead to increased parasitic capacitances, which slow down operation speeds, necessitating methods to reduce parasitic capacitance and improve reliability.
Innovation Solution
A method of fabricating semiconductor devices involves forming an interlayer insulating layer with varying pore densities, using a deposition process with different supply rates of silicon, organic, and porogen gases, and subsequent etching to create air gaps between conductive patterns, thereby reducing parasitic capacitance and enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of metal interconnections is reduced to increase integration capacity, then the capacity of semiconductor devices is improved, but parasitic capacitances increase and operation speeds are reduced
Solution Approach 1:
The patent applies porous low-k dielectric materials in the interlayer insulating structure to reduce parasitic capacitance. The porous structure with controlled pore density provides lower dielectric constant, which directly reduces the capacitive coupling between closely-spaced interconnections, thereby maintaining high operation speeds despite reduced pitch for increased integration capacity.
Solution Approach 2:
The patent implements a multi-layer interlayer insulating structure with varying pore densities in different regions. The first portion has a first pore density, the second portion has a second pore density, and the third portion has a third pore density, creating local variations in dielectric properties. This local quality optimization allows different regions to be tuned for specific electrical performance requirements, reducing overall parasitic capacitance while maintaining signal integrity for high-speed operation.
2Productivity
If the pitch of metal interconnections is reduced to increase integration capacity, then the capacity of semiconductor devices is improved, but parasitic capacitances increase
Solution Approach 1:
The patent utilizes porous low-k dielectric materials with controlled pore densities to reduce parasitic capacitance. The porous structure provides lower dielectric constant compared to conventional dense dielectrics, directly reducing the harmful capacitive effects between adjacent interconnections while allowing for higher integration density.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) by controlling pore density variations across different portions of the interlayer insulating structure. By adjusting the pore density from the first portion to the third portion, the patent optimizes the dielectric properties to minimize parasitic capacitance, enabling reduced interconnection pitch without the usual capacitance penalty.
3Ease of manufacture
If a uniform interlayer insulating layer is used, then the manufacturing process is simple, but the parasitic capacitance cannot be effectively reduced
Solution Approach 1:
The patent implements a multi-layer interlayer insulating structure with varying pore densities in different regions. The first portion has a first pore density, the second portion has a second pore density, and the third portion has a third pore density, creating local variations in dielectric properties. This local quality optimization allows different regions to be tuned for specific electrical performance requirements, reducing overall parasitic capacitance while maintaining signal integrity for high-speed operation.
Solution Approach 2:
The patent segments the interlayer insulating layer into multiple portions (first, second, and third portions) with different pore densities. This segmentation allows each layer to be optimized for specific functions, with the varying pore densities providing graded dielectric properties that effectively reduce parasitic capacitance while maintaining manufacturing feasibility through sequential deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance and improves the operation speed of semiconductor devices by creating air gaps through controlled pore density and etching, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
forming the interlayer insulating layer may be performed by a deposition process having a first deposition duration and a second deposition duration. The deposition process being performed by using a silicon precursor gas, an organic precursor gas, and a porogen gas
Implementation Method 2
forming the pores may include: applying heat or an ultraviolet ray to the interlayer insulating layer to remove a hydrocarbon material included in the porogen portions
Implementation Method 3
forming the pores may include: applying heat or an ultraviolet ray to the interlayer insulating layer to remove a hydrocarbon material included in the porogen portions
Implementation Method 4
etching the third portion of the interlayer insulating layer to reduce a height of the interlayer insulating layer
Data Source
AI summary
The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.