Porous-Region LDMOS Structure for Breakdown Field Control
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Solution Overview
Problem
LDMOSFETs experience performance degradation with device size scaling and operation at higher voltages, leading to reduced drain-to-source breakdown voltage (BVdss) and transconductance (Gm) due to the tradeoff between performance improvement, size scaling, and power consumption in modern integrated circuit design.
Innovation Solution
Incorporating a porous semiconductor region adjacent to an isolation structure within the semiconductor device, which modifies the electric field and improves both BVdss and Gm by forming a semiconductor structure with a porous region positioned near the isolation structure, such as a shallow trench isolation (STI) structure, in the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If LDMOSFETs are scaled down in size to improve integration density, then device size is reduced, but drain-to-source breakdown voltage (BVdss) and transconductance (Gm) deteriorate
Solution Approach 1:
The patent introduces a porous region with distinct physical properties (lower density, modified electric field characteristics) located specifically in the drift region adjacent to the isolation structure. This local modification of material quality allows the device to maintain high BVdss in the critical breakdown region while the overall device size is reduced, resolving the contradiction between size scaling and voltage breakdown performance
Solution Approach 2:
The patent changes the physical and electrical parameters of the semiconductor material by creating a porous structure with controlled porosity (e.g., 30-70% void volume). This parameter change modifies the electric field distribution and carrier transport characteristics, enabling the device to achieve improved BVdss and Gm despite size reduction, thus resolving the contradiction between device scaling and performance maintenance
2Power
If LDMOSFETs operate at higher voltages to improve power output, then power output is increased, but performance degradation occurs including reduced BVdss and Gm
Solution Approach 1:
The porous region is strategically positioned in the drift region where high electric fields occur during high-voltage operation. This local modification optimizes the electric field distribution specifically in the high-stress region, allowing the device to operate at higher voltages with improved or maintained Gm, thus resolving the contradiction between power output and transconductance degradation
Solution Approach 2:
The patent creates a composite structure combining dense semiconductor material with porous semiconductor material in the drift region. This composite structure leverages the advantages of both materials: the dense region provides mechanical strength and carrier supply, while the porous region provides optimized electric field control and reduced hot carrier effects, enabling high-voltage operation with maintained transconductance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The presence of the porous region enhances the semiconductor device's performance by increasing BVdss and Gm, effectively addressing the performance degradation issues faced by LDMOSFETs during size scaling and higher voltage operations.
Implementation Method 1
the porous region can modify an electric field around the isolation structure and can thereby improve device performance
Data Source
AI summary
Disclosed are embodiments of a semiconductor structure including a semiconductor device with an active device region and, within the active device region, porous semiconductor material adjacent to an isolation structure. In some embodiments, the semiconductor device can be a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). The LDMOSFET can include an active device region, a well region within the active device region and, within the well region, an isolation structure, a porous region immediately adjacent to the isolation structure, and a drain drift region that borders the isolation structure (e.g., between a channel region and a drain region). The porous region can modify the electric field in the drain drift region around the isolation structure and, as a result, can improve both drain-to-source breakdown voltage (BVdss) and transconductance (Gm) of the device. Also disclosed are method embodiments for forming the semiconductor structure.