Porous Oxide Capacitor Stack Planarization for Low-ESR Integration
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Solution Overview
Problem
Silicon passive integration technologies face challenges with high Equivalent Series Resistance (ESR) and limited capacitance density due to the thickness of porous anodic alumina layers, which can lead to cracks and non-planar topology issues during the anodizing process, affecting the functionality of subsequent MIM structures and interconnections.
Innovation Solution
A method involving the use of a liner and filler material to compensate for the height difference between anodized and non-anodized metal regions, where the liner material is selectively etched to expose the anodic porous oxide region, allowing for planarization and preventing cracks, while the filler material ensures a flush surface for subsequent deposition steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask is used to delimit the anodized region, then the porous region can be formed with precise boundaries, but the hard mask develops cracks during anodizing due to volume expansion, compromising device reliability
Solution Approach 1:
The patent removes the hard mask after anodizing is complete, extracting the masking function only when needed. This eliminates the hard mask's presence during subsequent processing steps that would be affected by cracks, while still achieving precise porous region boundaries during the anodizing process itself.
Solution Approach 2:
The hard mask is applied before anodizing to define the porous region boundaries, performing its delimiting function in advance. After serving this preliminary purpose, it is removed, preventing crack-related issues from affecting later device fabrication steps.
2Quantity of substance
If the porous region is formed thicker to increase capacitance density, then energy storage capability improves, but the height difference between anodized and non-anodized regions increases, causing non-planar topology that affects subsequent interconnection deposition
Solution Approach 1:
The patent introduces a vertical filler layer to compensate for the height difference created by thick porous alumina. This adds a dimension (vertical filling) to solve the planarity problem, allowing thick porous regions for high capacitance while maintaining a planar top surface for subsequent interconnection deposition.
Solution Approach 2:
The filler material is applied locally only to the non-anodized metal regions that are lower than the porous alumina surface. This local compensation creates a planar overall surface while preserving the thick porous region necessary for high capacitance density.
3Reliability
If the porous alumina layer is made thicker to reduce ESR, then electrical performance improves, but the anodizing process causes greater volume expansion, increasing the height difference and creating more severe non-planar topology
Solution Approach 1:
The filler layer compensates for the increased height difference resulting from thicker porous alumina formation. By adding vertical material to the lower regions, it maintains surface planarity even when the porous alumina thickness is increased to reduce ESR.
Solution Approach 2:
The patent changes the physical state and composition of the surface by introducing filler material, transforming the non-planar topology into a planar surface. This parameter change (from non-planar to planar) enables thicker porous alumina for ESR reduction without compromising subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a substantially planar electrical device with reduced ESR and improved capacitance density, preventing cracks and ensuring reliable subsequent deposition steps, such as forming interconnections and capacitors, by eliminating the height difference and sealing pores.
Implementation Method 1
The porous region results from anodizing a thin layer of metal, such as aluminum, deposited above the substrate. The anodizing converts the aluminum layer into porous anodic alumina.
Implementation Method 2
The anodizing converts the aluminum layer into porous anodic alumina.
Implementation Method 3
The porous region has a volume which is about 20% more than its initial pre-anodizing volume. Consequently, and because it can only grow upwards, the porous region PR is thicker than the aluminum layer AL, and there is a height difference h between the top surfaces of the two layers
Data Source
AI summary
A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.