Porous PID Mitigation Layer for Plasma-Damaged Gate Dielectrics
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Solution Overview
Problem
Plasma processes used in integrated chip fabrication cause plasma-induced damage (PID) to gate dielectrics, leading to high gate leakage currents and device failure, particularly in core NMOS/PMOS devices, which are challenging to meet reliability qualifications.
Innovation Solution
A plasma-induced damage mitigation layer, formed using a high-pressure plasma deposition process, is introduced to reduce plasma-induced damage by increasing ion collisions and forming a porous structure with a conductive material like titanium nitride, preventing charged particles from flowing through lower interconnects and mitigating damage during the formation of overlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma processes are used to form conductive interconnects, then manufacturing precision and productivity are improved, but plasma-induced damage occurs causing high gate leakage currents and device failure
Solution Approach 1:
A plasma-induced damage mitigation layer is introduced as an intermediary component between the plasma environment and the gate dielectric. This layer absorbs the harmful effects of plasma charging, preventing direct damage to the gate dielectric while allowing the plasma process to continue for efficient interconnect formation. The mitigation layer acts as a buffer that mediates the interaction between plasma and sensitive device structures.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the dielectric layer by forming a plasma-induced damage mitigation layer with specific properties (conductive material, porous structure, specific thickness). These parameter changes enable the layer to withstand plasma charging effects while maintaining its protective function, thus resolving the contradiction between using plasma processes and preventing device damage.
2Reliability
If plasma deposition is performed at high pressure, then a porous structure is formed that mitigates plasma-induced damage, but the deposition process becomes more complex
Solution Approach 1:
The patent utilizes parameter changes in the plasma deposition process, specifically operating at elevated pressures (e.g., 10-100 mTorr) to control the morphology and density of the deposited mitigation layer. This pressure parameter change naturally produces a porous structure that is effective at mitigating plasma damage, transforming a process complexity into a beneficial structural feature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PID mitigation layer effectively reduces plasma-induced damage, improving the reliability of integrated chips by minimizing gate leakage currents and enhancing the performance of NMOS/PMOS devices, with less than 1% failure rate for PMOS devices and maintaining consistent gate leakage for all NMOS devices.
Implementation Method 1
A plasma-induced damage mitigation layer, formed using a high-pressure plasma deposition process, is introduced to reduce plasma-induced damage
Implementation Method 2
increasing ion collisions and forming a porous structure with a conductive material like titanium nitride
Implementation Method 3
forming a porous structure with a conductive material like titanium nitride, preventing charged particles from flowing through lower interconnects
Data Source
AI summary
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.