Programmable Resistive Memory Structure With Porous Layer
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Solution Overview
Problem
Existing techniques for non-volatile memory cells, such as phase change memories and solid electrolyte-based programmable resistive memory elements, face challenges related to high photolithography steps and complexity, limiting integration with logic circuits and achieving high density, rapid access, and low power consumption.
Innovation Solution
A memory structure with an access transistor connected in series with a programmable resistive element, featuring a semiconductor substrate with an insulating layer, a porous material layer, and a metallic layer that allows controlled diffusion of metal ions through an electric field and temperature, enabling efficient programming and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase change memory or solid electrolyte-based programmable resistive memory elements are used, then non-volatile memory functionality is achieved, but the number of photolithography steps increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts the programmable resistive element from complex multi-step photolithography processes and implements it using a simpler structure with a semiconductor substrate, insulating layer with cavity, porous material layer, and metallic layer. This extraction reduces manufacturing complexity while maintaining non-volatile memory functionality.
Solution Approach 2:
The patent changes the material parameters and structural configuration from conventional phase change memory materials to a combination of porous material (such as silicon oxycarbide or germanium oxycarbide) and metallic material (such as copper). This parameter change enables programmable resistive behavior with fewer photolithography steps.
2Reliability
If phase change memory or solid electrolyte-based programmable resistive memory elements are used, then non-volatile memory functionality is achieved, but integration with logic circuits is limited
Solution Approach 1:
The patent creates a universal memory cell structure that can be integrated with standard CMOS logic circuits. The use of conventional semiconductor substrate, insulating layers, and metallic layers compatible with standard fabrication processes enables full system integration while maintaining non-volatile memory functionality.
Solution Approach 2:
The porous material layer acts as an intermediary between the metallic layer and the semiconductor substrate, enabling controlled diffusion of metal ions while providing a structure compatible with standard CMOS fabrication processes. This intermediary structure facilitates integration with logic circuits.
3Reliability
If conventional programmable resistive memory structures are used, then memory functionality is achieved, but power consumption is high
Solution Approach 1:
The patent uses porous material (such as silicon oxycarbide or germanium oxycarbide) as the second layer, which enables controlled diffusion of metal ions at lower energy levels. The porous structure provides diffusion pathways that reduce the energy required for programming operations compared to dense material structures.
Solution Approach 2:
The patent changes the material composition to porous material with specific properties that enable low-power operation. The metallic material (such as copper) combined with porous material creates a system where metal ion diffusion can be controlled with lower applied voltages and currents, reducing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the integration of non-volatile memory cells with logic circuits, achieving high density, rapid memory access, and low power consumption, while simplifying the manufacturing process and reducing the number of photolithography steps.
Implementation Method 1
Diffusion of metallic ions within the second layer is controlled by the joint action of an electric field and temperature
Implementation Method 2
Diffusion of metallic ions within the second layer is controlled by the joint action of an electric field and temperature
Implementation Method 3
Phase change memories (PCM) are based on the use of chalcogenide alloys (Ge2, Se2, Te2) which present two possible phases, respectively disorderly (amorphous) or more orderly (crystalline), distinguished from one another by different resistivity. The transition from one phase to another is controlled by a cycle of heating/cooling
Data Source
AI summary
A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described.