Porous Semiconductor STI for Faster IC Isolation Processing
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Solution Overview
Problem
Conventional shallow trench isolation (STI) and deep trench isolation (DTI) processes in semiconductor fabrication are time-consuming and costly, hindering the speed and efficiency of front-end-of-line (FEOL) processing.
Innovation Solution
The development of porous semiconductor (π-Semi) isolation structures, which are formed through electrochemical etching of crystalline semiconductor layers, providing excellent electrical insulation and hole trapping capabilities. These structures can be fabricated as either pre-FET or post-FET structures, reducing the complexity and cost of IC fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching and filling techniques are used to form STI structures, then electrical isolation between adjacent components is achieved, but the fabrication process becomes time-consuming and costly
Solution Approach 1:
The patent changes the material parameter from conventional dielectric materials to porous semiconductor material, which can be formed through electrochemical etching instead of conventional etching and filling. This parameter change enables direct formation of isolation structures with excellent electrical isolation properties while significantly reducing process time and complexity
Solution Approach 2:
The patent replaces the mechanical/chemical etching and dielectric filling process with an electrochemical etching process that directly forms porous semiconductor isolation structures. This substitution eliminates the need for separate etching, filling, and planarization steps, thereby improving fabrication speed while maintaining electrical isolation
2Reliability
If conventional etching and filling techniques are used to form STI structures, then electrical isolation is achieved, but the device complexity and fabrication cost increase
Solution Approach 1:
The patent merges multiple conventional process steps (etching, dielectric filling, planarization) into a single electrochemical etching step that directly forms porous semiconductor isolation structures. This consolidation reduces process complexity while achieving the same electrical isolation function
Solution Approach 2:
By changing the material parameter to porous semiconductor and the process parameter to electrochemical etching, the patent simplifies the overall fabrication process while maintaining excellent electrical isolation properties, thereby reducing device complexity
3Productivity
If porous semiconductor structures are formed through electrochemical etching, then fabrication speed increases and cost decreases, but the structural complexity of the semiconductor layer increases
Solution Approach 1:
The patent utilizes porous semiconductor material formed through electrochemical etching to create isolation structures. The porous structure provides excellent electrical isolation properties while enabling direct formation through a single etching step, thereby improving fabrication speed despite the increased structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of π-Semi isolation structures significantly accelerates FEOL processing and decreases the overall cost of IC fabrication by eliminating the need for time-consuming etching and filling processes, while maintaining excellent electrical isolation.
Implementation Method 1
exposed portions of a crystalline semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures
Implementation Method 2
The characteristics of π-Semi, particularly mesoporous π-Semi and microporous-Semi, include good electrical insulation
Data Source
AI summary
Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (π-Semi) isolation structures such as shallow trench isolation (STI) and/or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures; in essence, the in situ semiconductor is restructured to π-Semi. The characteristics of π-Semi, particularly mesoporous π-Semi and microporous π-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, π-Semi used for STI and/or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET”π-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a “post-FET”π-Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.