Porous Semiconductor IC Structure for Low-Parasitic ESD Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) face reliability issues due to electrostatic discharge (ESD) and performance degradation caused by parasitic capacitances and bipolar junction transistors formed in existing ESD protection devices, such as semiconductor controlled rectifiers (SCRs), which affect RF circuitry performance.
Innovation Solution
A structure incorporating a porous semiconductor region with a cavity and semiconductor layer, where wells and doped regions of different conductivity types are formed, reducing parasitic capacitances and bipolar junction transistors by acting as a high-resistivity layer between the device and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor controlled rectifiers (SCRs) are used for ESD protection, then ESD protection capability is improved, but parasitic capacitances and bipolar junction transistors are formed which degrade RF performance
Solution Approach 1:
The patent extracts and removes the harmful porous semiconductor region after it has served its protective function during ESD events. The porous region is formed temporarily to provide ESD protection and then selectively removed through etch holes, leaving only the necessary doped regions and wells. This extraction eliminates the parasitic capacitances and bipolar junction transistors that would otherwise degrade RF performance while maintaining the ESD protection capability during critical events.
Solution Approach 2:
The patent utilizes a porous semiconductor region as a temporary protective structure during ESD events. The porous region has high resistivity that prevents parasitic BJT formation and reduces capacitive loading. After serving its protective purpose, the porous region is selectively removed through etch holes to eliminate harmful parasitic effects for subsequent RF operation.
2Reliability
If ESD protection devices are implemented in RF devices, then ESD protection is improved, but RF performance is degraded due to capacitive loading and poor harmonics
Solution Approach 1:
The patent extracts the porous semiconductor region after ESD protection is achieved, removing the source of capacitive loading and harmonic distortion. The porous region is formed to provide ESD protection, then selectively etched away through patterned holes to eliminate RF performance degradation while maintaining the protective function.
Solution Approach 2:
The patent changes the physical state of the semiconductor region from porous to removed, transforming the structure from a protective element to an eliminated harmful element. The porous region provides high resistivity for ESD protection, then is removed to restore normal RF electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and performance of ICs by eliminating parasitic capacitances and bipolar junction transistors, thereby improving ESD protection without degrading RF performance.
Implementation Method 1
incorporating a high-resistivity porous semiconductor region between the device and the substrate
Implementation Method 2
a first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity
Data Source
AI summary
Embodiments of the disclosure provide a structure including a semiconductor substrate. The semiconductor substrate includes a porous semiconductor region, the porous semiconductor region including a cavity. The cavity includes a semiconductor layer therein. The porous semiconductor further includes a device. The device includes a first well at least partially in the semiconductor layer and a second well at least partially in the semiconductor layer and positioned laterally immediately adjacent the first well. The device further includes a first doped region abutting the first well; and a second doped region abutting the second well, wherein the first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity.