Porous Semiconductor Handle Substrate for RF Harmonic Reduction
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Solution Overview
Problem
Current mobile RF transceivers face design complexity and increased RF losses due to artificial harmonics, which are not adequately reduced by conventional silicon on insulator technology, and the use of high resistivity handle wafers is costly.
Innovation Solution
A porous semiconductor handle substrate is created by electro-chemically etching a bulk semiconductor wafer to form a trap rich layer, which reduces RF harmonics and increases linearity without the need for expensive high resistivity wafers, using a process that controls porosity and doping for effective device isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon on insulator technology is used, then device isolation is improved, but RF harmonics are not sufficiently reduced
Solution Approach 1:
The patent employs a porous silicon layer formed through electrochemical etching as the handle substrate. This porous structure creates a trap-rich environment that effectively reduces RF harmonics while maintaining device isolation. The porous nature of the silicon allows it to function as both an electrical isolator and a harmonic reducer, resolving the contradiction between these two requirements.
Solution Approach 2:
The patent changes the physical and electrical parameters of the handle substrate by creating a porous structure with controlled porosity (e.g., 30-70%) and specific doping concentrations. This transformation from solid silicon to porous silicon fundamentally alters the substrate's electrical characteristics, enabling it to reduce RF harmonics while maintaining isolation properties.
2Reliability
If high resistivity handle wafers are used, then RF performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive high resistivity handle wafers with a cost-effective porous silicon layer formed on standard silicon substrates. The porous silicon layer, created through electrochemical etching and doping processes, provides the necessary RF performance at a fraction of the cost of conventional high resistivity wafers, making the solution economically viable.
Solution Approach 2:
The patent creates a composite structure consisting of a porous silicon layer with specific porosity and doping characteristics formed on a silicon substrate. This composite material combines the cost-effectiveness of standard silicon with the RF performance benefits of high resistivity materials, achieving both affordability and performance.
3Reliability
If SOI substrates are used, then parasitic capacitance is reduced, but artificial harmonics increase
Solution Approach 1:
The patent uses a porous silicon layer as the handle substrate beneath the SOI structure. The porous structure creates a trap-rich environment that reduces artificial harmonics generated by the SOI devices, while the SOI layer itself maintains low parasitic capacitance. This combination resolves the contradiction between these two competing requirements.
Solution Approach 2:
The porous silicon layer acts as an intermediary between the SOI active devices and the bulk substrate. It mediates the interaction by providing electrical isolation like the BOX layer while simultaneously reducing artificial harmonics through its trap-rich porous structure, thereby resolving the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The porous silicon layer effectively reduces RF harmonics and improves device linearity, providing a cost-effective solution for RF device performance enhancement by acting as a trap rich layer without the high cost of conventional trap rich silicon handle wafers.
Implementation Method 1
A porous semiconductor handle substrate is created by electro-chemically etching a bulk semiconductor wafer to form a trap rich layer
Implementation Method 2
The porous silicon layer effectively reduces RF harmonics and improves device linearity
Data Source
AI summary
An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.