Porous Semiconductor Layer for RF Isolation in Bulk ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bulk semiconductor substrates with high resistivity polycrystalline isolation layers exhibit higher harmonics and substrate leakage current compared to semiconductor-on-insulator (SOI) substrates, limiting their performance in radio frequency (RF) device applications.
Innovation Solution
An integrated circuit (IC) structure is developed with a porous semiconductor layer between trench isolations and a polycrystalline isolation layer under active devices on a bulk semiconductor substrate, providing additional isolation and reducing harmonics and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity polycrystalline isolation layer is used in bulk semiconductor substrates, then additional isolation is provided, but harmonics and substrate leakage current increase
Solution Approach 1:
The patent applies porous semiconductor material as an isolation layer between the trench isolation and the polycrystalline isolation layer. The porous structure provides additional electrical isolation to reduce substrate leakage current and harmonics while maintaining device performance, effectively resolving the contradiction between isolation performance and harmful electrical effects.
Solution Approach 2:
The patent creates a composite isolation structure combining multiple materials: trench isolation (dielectric), porous semiconductor layer, and polycrystalline isolation layer. This composite approach leverages the advantages of each material to achieve both good isolation performance and reduced harmonics and leakage current in bulk semiconductor substrates.
2Object-generated harmful factors
If SOI substrate is used, then harmonics and leakage current are reduced, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive SOI substrates with a cost-effective bulk semiconductor substrate combined with a porous isolation layer. This approach achieves SOI-like performance characteristics (reduced harmonics and leakage) using cheaper bulk substrate technology, effectively applying the principle of using economical alternatives that deliver comparable performance.
Solution Approach 2:
By introducing porous semiconductor material as an isolation layer in bulk substrates, the patent replicates the electrical isolation characteristics of SOI substrates without requiring the expensive SOI structure, thereby achieving similar performance benefits at lower manufacturing cost.
3Reliability
If trench isolation is used to electrically isolate active devices, then device isolation is achieved, but additional isolation layers are needed to reduce harmonics and parasitic losses
Solution Approach 1:
The patent segments the isolation function into multiple distinct layers: the trench isolation provides primary device-to-device isolation, while the additional porous semiconductor layer and polycrystalline isolation layer provide secondary isolation specifically targeted at reducing harmonics and parasitic losses. This segmentation allows each layer to optimize for its specific function.
Solution Approach 2:
The porous semiconductor layer acts as an intermediary isolation layer between the trench isolation and the substrate. It provides additional electrical isolation that specifically addresses harmonics and parasitic losses without interfering with the primary isolation function of the trench isolation, effectively mediating between different isolation requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IC structure achieves better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, effective permittivity, and attenuation compared to SOI substrate devices, while using a lower cost, low resistivity bulk semiconductor substrate, thus enhancing RF device performance.
Implementation Method 1
a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer
Data Source
AI summary
An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.