Porous Silicon Starting Structure for Low-Voltage Semiconductor Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing technologies face challenges in forming semiconductor protection devices like Shockley diodes with desired breakdown voltages below 10 volts, as the doping levels required for proper operation are not compatible, and it is difficult to accurately adjust these levels for monolithic formation.
Innovation Solution
A starting structure using a thin porous silicon layer is integrated between two conductive regions in a semiconductor substrate, allowing for fine adjustment of threshold voltage and enabling the formation of vertical semiconductor components with low on-state voltage drop and improved dynamic performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping levels are used for thyristor operation, then proper thyristor operation is achieved, but formation of avalanche diode with desired breakdown voltage becomes difficult
Solution Approach 1:
The patent applies local quality by creating a heavily-doped N-type ring region at the periphery of the P-type well, distinct from the main N-type layer. This localized heavily-doped region specifically forms the avalanche diode junction with the P-type well, while the main N-type layer maintains appropriate doping for thyristor operation. The spatial separation of doping levels allows independent optimization of both thyristor and avalanche diode characteristics.
Solution Approach 2:
The P-type well acts as an intermediary element between the N-type substrate and the N-type layer. By introducing this intermediate P-type region, the patent enables the formation of two distinct junctions: one between the P-type well and N-type substrate, and another between the P-type well and the heavily-doped N-type ring, thereby facilitating both thyristor and avalanche diode functionality.
2Productivity
If N-type region thickness is reduced for low turn-on voltage, then dynamic performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the N-type layer and the heavily-doped N-type ring into a single manufacturing step. Both regions are formed simultaneously through co-implantation or co-diffusion processes, eliminating the need for separate fabrication steps. This integration maintains the thin N-type region structure for improved dynamic performance while simplifying the overall manufacturing process.
3Manufacturing precision
If breakdown voltage is reduced below 10 volts, then protection threshold is lowered, but doping level adjustment becomes difficult
Solution Approach 1:
The patent achieves breakdown voltages below 10 volts by significantly increasing the doping concentration of the N-type ring region to greater than 10^18 atoms/cm³. This parameter change in doping concentration fundamentally alters the electrical characteristics of the avalanche diode junction, enabling low breakdown voltages that were previously difficult to achieve with conventional doping levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise adjustment of threshold voltages below 10 volts, enhancing the dynamic performance and reducing stray capacitance and temperature dependence of Shockley diodes, making them suitable for monolithic integration on silicon substrates.
Implementation Method 1
the junction between N+-type ring 17 and P-type well 12 plays the role of avalanche diode Z of FIG. 2A. When the diode corresponding to the junction between N+-type ring 17 and P-type well 12 should have a relatively low avalanche voltage
Data Source
AI summary
A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.


