Port Affinity Router SMP Cache Coherence Bottleneck
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Solution Overview
Problem
Network routers face performance issues due to the need for frequent data retrieval from shared memory, leading to inefficiencies in packet processing, especially when threads are reassigned across processors, causing cache coherence problems and increased processing cycles.
Innovation Solution
Implementing a router with Symmetric Multiprocessors (SMPs) that have 'port affinity' between processors and ports, where interfaces are subdivided and assigned to specific processors to minimize cache coherence operations and optimize data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple threads are assigned to different processors for parallel packet processing, then processing throughput is improved, but cache coherence operations and lock contention increase
Solution Approach 1:
The router interfaces are divided into distinct sets, with each set assigned to a specific processor. This segmentation ensures that packets arriving at different interfaces are processed by different processors, reducing cache coherence operations and lock contention while maintaining parallel processing throughput.
Solution Approach 2:
Each processor is assigned specific interfaces with which it has local affinity, allowing it to efficiently process packets from those interfaces using its local cache. This local quality assignment optimizes data access patterns and reduces the need for cross-processor cache coherence operations.
2Adaptability or versatility
If threads are reassigned across processors to balance load, then processor load balancing is improved, but data access performance deteriorates due to cache misses
Solution Approach 1:
The interface-to-processor assignment is established in advance through manual setup or dynamic algorithms, creating a predetermined mapping that optimizes data access. This preliminary action ensures that packets from specific interfaces are consistently handled by the same processor, improving data access speed while load balancing is achieved through the assignment strategy itself.
3Speed
If all packets are processed by a single processor, then data access performance is maintained, but processing capacity and scalability are limited
Solution Approach 1:
The processing workload is segmented across multiple processors, with each processor responsible for packets from specific interfaces. This segmentation enables parallel processing capacity while maintaining efficient data access patterns, as each processor handles packets from its assigned interfaces using its local cache.
Solution Approach 2:
The system transitions from single-processor sequential processing to multi-processor parallel processing by adding the processor dimension to the packet handling architecture. This dimensional change enables both high processing capacity and maintained data access performance through careful interface-to-processor affinity assignment.
Data Source
AI summary
A router that includes a plurality of processors (SMPs) where there is “affinity” between particular processors and particular interfaces: Each of the router's interfaces are assigned to one of the processors. A packet arriving at a particular interface will be handled by the processor having an affinity to that particular interface. If the packet's egress is on an interface assigned to the same processor, then the output process will also be handled by that processor. If the egress interface has an affinity to a different processor, then the packet is handed over to the other processor for egress. The data structures that must be retrieved from memory to handle a packet are often associated with the interfaces through which the packet passes. Thus, having a particular processor handle all the packets that pass through a particular interface insures that the data structures needed to handle the packets will more likely be stored in the processor's cache and less likely be the object of inter-processor lock contention.