Port Controller Reprogramming via External Debug Port

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Solution Overview

Problem

Conventional methods for reprogramming port controllers, such as USB Type-C interfaces, are often time-consuming, inconvenient, and costly, requiring opening of the device chassis or relying on a host processor that may be unbootable or infected with malware.

Innovation Solution

A debug tool and debug computing system are used to reprogram the port controller via an external port, allowing firmware updates without opening the chassis, using a device firmware update application on a system on chip to direct the reprogramming and enabling power from an external source, even when the device lacks internal power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a specialized tool is plugged into a JTAG port to reprogram the port controller chip, then the firmware can be updated, but the device chassis must be opened which is time-consuming and inconvenient

Engineering Contradiction:
Improvefirmware update capabilityVSAvoidaccess convenience
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces an intermediary debugging interface that connects the port controller chip to an external debugging tool through existing communication interfaces (USB, UART, I2C) rather than requiring direct physical access to internal JTAG ports. This intermediary layer allows firmware updates to be performed through external ports that are already accessible on the device chassis, eliminating the need to open the device while maintaining reliable firmware update capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the host processor runs DFU software to program new firmware into the port controller chip, then the update can be performed internally, but the solution is unsuitable when the device is unbootable, lacks power or is infected with malware

Engineering Contradiction:
Improveupdate process integrationVSAvoidoperational condition compatibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements a self-service mechanism where the port controller chip can be reprogrammed independently of the host processor's operational state. By using a debugging interface that directly accesses the port controller chip through external ports, the system can perform firmware updates even when the host processor is unbootable, lacks power, or is infected with malware. The port controller chip serves itself by accepting firmware updates through its own dedicated debugging interface without requiring the host processor to be functional.

Inventive Principle:
Principle #25Self-service

3Reliability

If conventional reprogramming methods are used, then firmware updates can be performed, but the process is time-consuming and costly

Engineering Contradiction:
Improvefirmware update functionalityVSAvoidreprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-configuring the port controller chip with a debugging interface that is always accessible through external ports. This preliminary setup allows firmware updates to be performed immediately when needed, without requiring preliminary disassembly of the device or complex setup procedures. The debugging interface is prepared in advance and can be activated on-demand, significantly reducing the time required for firmware updates while maintaining reliable update functionality.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3238067B1Reprogramming a port controller via its own external port
Publication Date: 2023.06.14 INTEL CORP
  • EP3238067B1 patent drawingFigure 1
  • EP3238067B1 patent drawingFigure 2
  • EP3238067B1 patent drawingFigure 3A~3D

AI summary

Systems and methods may provide for a debug tool including a debug port and a controller including logic to send, via the debug port, a debug mode request to an external port of a target device. Additionally, the target device may include a connector having the external port and a port controller coupled to the external port, wherein the port controller includes logic to detect the debug mode request via the external port, activate a program path between the external port and the port controller in response to the debug mode request, and process one or more commands received via the program path. In one example, the target device further includes a multiplexer coupled to the external port and the port controller, wherein the logic is to send a routing signal to the multiplexer to activate the program path.