IC Port Initialization with Parity Supervision for Stuck-At Detection
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Solution Overview
Problem
Integrated circuits in harsh environments face data integrity issues due to disturbances and latent defects, which existing solutions like redundancy and parity monitoring are costly and inefficient, especially in handling 'stuck at' conditions on control signals.
Innovation Solution
A port supervising device that operates in a background loop to monitor and check data integrity across multiple ports, generating error signals for inconsistencies and handling write operations by generating parity bits, thus reducing the load on the central processing unit and improving system security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant components are used to supervise port data integrity, then reliability is improved, but device complexity and silicon area increase significantly
Solution Approach 1:
The patent introduces a port supervising device as an intermediary component between the CPU and multiple ports. This supervisor handles parity generation, verification, and error detection centrally, eliminating the need for redundant supervision logic in each port or the CPU itself. The supervisor acts as a mediator that manages data integrity for all ports through a unified mechanism, reducing overall system complexity while maintaining reliability.
Solution Approach 2:
The port supervising device serves multiple functions within a single component: it generates parity bits for write operations, verifies parity for read operations, detects errors including stuck-at conditions, and manages initialization sequences. This multi-functional approach consolidates what would otherwise require separate redundant components, reducing silicon area and device complexity while maintaining comprehensive data integrity supervision.
2Reliability
If parity bits are used for each port, then reliability is improved, but manufacturing cost and silicon area increase
Solution Approach 1:
The patent merges the parity generation and verification functions into a single port supervising device that serves all ports. Instead of implementing separate parity mechanisms for each port or for every data bus transaction, the supervisor consolidates these functions centrally. This merging reduces the total number of parity bits required and eliminates redundant manufacturing complexity, lowering production costs while maintaining data integrity across all ports.
3Reliability
If the CPU performs all parity checks and supervision, then reliability is improved, but productivity and CPU performance decrease due to increased processing load
Solution Approach 1:
The patent segments the data integrity supervision function from the CPU by introducing a dedicated port supervising device. The CPU retains its primary processing functions while the supervisor handles parity generation, verification, and error detection independently. This segmentation allows the CPU to operate at full speed without being burdened by supervision tasks, maintaining both reliability and productivity.
Solution Approach 2:
The port supervising device operates autonomously to perform parity checks and error detection without requiring CPU intervention for each operation. The supervisor self-manages the supervision of all ports, generating parity bits during writes and verifying them during reads independently. This self-service capability eliminates the processing overhead on the CPU, maintaining high productivity while ensuring data integrity.
4Ease of operation
If asynchronous reset sequences are used for port initialization, then ease of operation is improved, but reliability decreases due to undetected stuck-at conditions
Solution Approach 1:
The patent implements feedback mechanisms within the port supervising device to detect stuck-at conditions during initialization. The supervisor monitors the initialization sequence and compares the actual port states against expected states. When a discrepancy is detected (indicating a stuck-at condition), the supervisor generates an error signal. This feedback loop maintains the simplicity of asynchronous reset operations while adding reliable error detection capability.
Solution Approach 2:
The port supervising device performs preliminary verification of initialization sequences before allowing normal operation to proceed. By checking port states and parity information during the initialization phase, the supervisor ensures that stuck-at conditions are detected early. This preliminary action maintains ease of operation while preventing undetected errors from propagating into system operation.
Data Source
AI summary
A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialization signal comprising port initialization data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialization signal comprising the port initialization data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialization signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialization data and the just obtained original one or more parity bits.